“Agile” Chip Building (CRAFT, ChipKit, Chip Gallery)

Bibliographic References tagged with “Agile” Chip Building (CRAFT, ChipKit, Chip Gallery)

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Thierry Tambe, David Brooks, and Gu-Yeon Wei. 2022. “Learnings from a HLS-Based High-Productivity Digital VLSI Flow”. In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22)
Thierry Tambe, David Brooks, and Gu-Yeon Wei. 2022. “Learnings from a HLS-Based High-Productivity Digital VLSI Flow”. In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22)
Paul Whatmough, Sae Lee, Hyunkwang Lee, Saketh Rama, David Brooks, and Gu Wei. 2017. “A 28nm SoC With a 1.2GHz 568nJ Prediction Sparse Deep-Neural-Network Engine With >0.1 Timing Error Rate Tolerance for IoT Applications”. In International Solid-State Circuits Conference. San Francisco, CA, USA
Paul Whatmough, Sae Lee, Hyunkwang Lee, Saketh Rama, David Brooks, and Gu Wei. 2017. “A 28nm SoC With a 1.2GHz 568nJ Prediction Sparse Deep-Neural-Network Engine With >0.1 Timing Error Rate Tolerance for IoT Applications”. In International Solid-State Circuits Conference. San Francisco, CA, USA
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Thierry Tambe, Rob Rutenbar, David Brooks, and Gu-Yeon Wei. 2020. “A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception Using Parallel Gibbs Sampling in 16nm”. In IEEE Symposium on VLSI Circuits (VLSI)
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Thierry Tambe, Rob Rutenbar, David Brooks, and Gu-Yeon Wei. 2020. “A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception Using Parallel Gibbs Sampling in 16nm”. In IEEE Symposium on VLSI Circuits (VLSI)
Sae Lee, Paul Whatmough, David Brooks, and Gu Wei. 2019. “A 16-Nm Always-on DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs”. IEEE Journal of Solid-State Circuits, 54, 7, Pp. 1982-92
Sae Lee, Paul Whatmough, David Brooks, and Gu Wei. 2019. “A 16-Nm Always-on DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs”. IEEE Journal of Solid-State Circuits, 54, 7, Pp. 1982-92
Paul Whatmough, Sae Lee, Marco Donato, Hsea Hsueh, Sam Xi, Udit Gupta, Lillian Pentecost, Glenn Ko, David Brooks, and Gu Wei. 2019. “A 16nm 25mm2 SoC With a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to EFPGA and Cache-Coherent Accelerators”. Symposium on VLSI Circuits
Paul Whatmough, Sae Lee, Marco Donato, Hsea Hsueh, Sam Xi, Udit Gupta, Lillian Pentecost, Glenn Ko, David Brooks, and Gu Wei. 2019. “A 16nm 25mm2 SoC With a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to EFPGA and Cache-Coherent Accelerators”. Symposium on VLSI Circuits
Sae Lee, Paul Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks, and Gu Wei. 2018. “A Wide Dynamic Range Sparse FC-DNN Processor With Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET”. ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference
Sae Lee, Paul Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks, and Gu Wei. 2018. “A Wide Dynamic Range Sparse FC-DNN Processor With Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET”. ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference
Paul Whatmough, Sae Lee, David Brooks, and Gu Wei. 2018. “DNN ENGINE: A 28-Nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications”. IEEE Journal of Solid-State Circuits (JSSC), 53, 9
Paul Whatmough, Sae Lee, David Brooks, and Gu Wei. 2018. “DNN ENGINE: A 28-Nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications”. IEEE Journal of Solid-State Circuits (JSSC), 53, 9
Paul Whatmough, Sae Lee, Sam Xi, Udit Gupta, Lillian Pentecost, Marco Donato, Hsea Hseuh, David Brooks, and Gu Wei. 2018. “SMIV: A 16nm SoC With Efficient and Flexible DNN Acceleration for Intelligent IoT Devices”. Hot Chips 30: A Symposium on High Performance Chips, 99, Pp. 1-1
Paul Whatmough, Sae Lee, Sam Xi, Udit Gupta, Lillian Pentecost, Marco Donato, Hsea Hseuh, David Brooks, and Gu Wei. 2018. “SMIV: A 16nm SoC With Efficient and Flexible DNN Acceleration for Intelligent IoT Devices”. Hot Chips 30: A Symposium on High Performance Chips, 99, Pp. 1-1
Paul Whatmough, Sae Lee, Niamh Mulholland, Patrick Hansen, Sreela Kodali, and David Brooks. 2017. “DNN ENGINE: A 16nm Sub-UJ Deep Neural Network Inference Accelerator for the Embedded Masses”. In Hot Chips 29: A Symposium on High Performance Chips
Paul Whatmough, Sae Lee, Niamh Mulholland, Patrick Hansen, Sreela Kodali, and David Brooks. 2017. “DNN ENGINE: A 16nm Sub-UJ Deep Neural Network Inference Accelerator for the Embedded Masses”. In Hot Chips 29: A Symposium on High Performance Chips
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Tambe Thierry, Rob Rutenbar, Gu Wei, and Gu Wei. 2020. “A Scalable Bayesian Inference Accelerator for Unsupervised Learning”. In IEEE Hot Chips 31 Symposium. Palo Alto, CA, USA
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Tambe Thierry, Rob Rutenbar, Gu Wei, and Gu Wei. 2020. “A Scalable Bayesian Inference Accelerator for Unsupervised Learning”. In IEEE Hot Chips 31 Symposium. Palo Alto, CA, USA