DeepRecSys provides an end-to-end infrastructure to study and optimize at-scale neural recommendation inference. The infrastructure is configurable across three main dimensions that represent different recommendation use cases: the load generator (query arrival patterns and size distributions), neural recommendation models, and underlying hardware platforms. DeepRecSys code available on GitHub.
EdgeBERT is a HW/SW co-design enabling sentence-level energy optimizations for latency-aware multi-task NLP inference. In this repo, we provide both the software and hardware modelings. EdgeBERT code available on GitHub.
An AXI-programmable hardware accelerator for attention-based seq-to-seq networks. FlexASR can be configured to accelerate end-to-end RNN, GRU or LSTM models with attention mechanisms (e.g. Listen-Attend-and-Spell models). It was designed in Synthesizable SystemC followed by high-level synthesis (HLS) in order to generate RTL.. FlexASR code available on GitHub.
gem5-Aladdin is an integration of the Aladdin accelerator simulator with the gem5 system simulator to enable simulation of end-to-end accelerated workloads on SoCs. You may download the code here. It is maintained by Sam Xi and Yakun Sophia Shao. gem5-Aladdin code available on GitHub.
NVMExplorer is a cross-stack design space exploration framework for evaluating and comparing on-chip memory solutions including emerging, embedded non-volatile memories. NVMExplorer code available on GitHub.
RecPipe provides an end-to-end system to study and jointly optimize recommendation models and hardware for at-scale inference. This repository provides the RecPipe infrastructure which is configuration across different models and hardware (general purpose and specialized accelerator) dimensions. The infrastructure enables judicious comparison of recommendation quality, inference latency, and system-throughput. RecPipe code available on GitHub.
A deep learning framework that enables end-to-end simulation of DL models on custom SoCs with a variety of hardware accelerators. SMAUG is designed to enable DNN researchers to rapidly evaluate different accelerator and SoC designs and perform hardware-software co-design. Simulation is powered by the gem5-Aladdin SoC simulator, allowing users to easily write new hardware accelerators and integrate them into SMAUG for testing and exploration. Smaug code available on GitHub.