Publications

2015
Sae Lee, Tao Tong, Xuang Zhang, David Brooks, and Gu Wei. 6/2015. “A 16-Core Voltage-Stacked System with an Integrated Switched-Capacitor DC-DC Converter.” In IEEE Symposium on VLSI Circuits (VLSIC), 99: Pp. 1-14. Kyoto, Japan. Publisher's VersionAbstract
A 16-core voltage-stacked IC integrated with a switched-capacitor DC-DC converter demonstrates efficient power delivery. To overcome inter-layer voltage noise issues, the test chip implements and evaluates the benefits of self-timed clocking and clock-phase interleaving. The integrated converter offers minimum voltage guarantees and further reduces voltage noise.
A 16-Core Voltage-Stacked System with an Integrated Switched-Capacitor DC-DC Converter
Yakun Shao, Brandon Reagen, Gu Wei, and David Brooks. 5/13/2015. “The aladdin approach to accelerator design and modeling.” IEEE Micro, 35, 3, Pp. 58–70. Publisher's VersionAbstract
Hardware specialization, in the form of datapath and control circuitry customized to particular algorithms or applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerators relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but also are slow and tedious to use, making large design space exploration infeasible. To overcome this problem, the authors developed Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrated its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9, 4.9, and 6.6 percent with respect to RTL implementations. Integrated with architecture-level general-purpose core and memory hierarchy simulators, Aladdin provides researchers with a fast but accurate way to model the power and performance of accelerators in an SoC environment.
The aladdin approach to accelerator design and modeling
Simone Campanoni, Glenn Holloway, Gu Wei, and David Brooks. 2/7/2015. “HELIX-UP: Relaxing Program Semantics to Unleash Parallelization.” In International Symposium on Code Generation and Optimization (CGO), Pp. 235–245. San Francisco, CA, USA. Publisher's VersionAbstract
Automatic generation of parallel code for general-purpose commodity processors is a challenging computational problem. Nevertheless, there is a lot of latent thread-level parallelism in the way sequential programs are actually used. To convert latent parallelism into performance gains, users may be willing to compromise on the quality of a programś results. We have developed a parallelizing compiler and runtime that substantially improve scalability by allowing parallelized code to briefly sidestep strict adherence to language semantics at run time. In addition to boosting performance, our approach limits the sensitivity of parallelized code to the parameters of target CPUs (such as core-to-core communication latency) and the accuracy of data dependence analysis.
HELIX-UP: Relaxing Program Semantics to Unleash Parallelization
Sam Xi, Hans Jacobson, Pradip Bose, Gu Wei, and David Brooks. 2/7/2015. “Quantifying Sources of Error in McPAT and Potential Impacts on Architectural Studies.” In International Symposium on High Performance Computer Architecture (HPCA). Publisher's VersionAbstract
Architectural power modeling tools are widely used by the computer architecture community for rapid evaluations of high-level design choices and design space explorations. Currently, McPAT is the de facto power model, but the literature does not yet contain a careful examination of its modeling accuracy. In addition, the issue of how greatly power modeling error can affect architectural-level studies has not been quantified before. In this work, we present the first rigorous assessment of McPAT’s core power and area models with a detailed, validated power modeling toolchain used in current industrial practice. We find that McPAT’s predictions can have significant error because some of the models are either incomplete, too high-level, or assume implementations of structures that differ from that of the core at hand. We demonstrate that large errors are possible when using McPAT’s dynamic power estimates in the context of voltage noise and thermal hotspots, but for steady-state properties, accurately modeling leakage power is more important. Based on our analysis, we are able to provide guidelines for creating accurate McPAT models, even without access to detailed industrial power modeling tools. We conclude that in spite of its accuracy gaps, McPAT is still a very useful tool for many architectural studies, and its limitations can often be adequately addressed for a given research study of interest.
Quantifying Sources of Error in McPAT and Potential Impacts on Architectural Studies
Vijay Reddi, Meeta Gupta, Glenn Holloway, Gu Wei, Michael Smith, and David Brooks. 2015. “Adaptive event-guided system and method for avoiding voltage emergencies”.Abstract
In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.
Adaptive event-guided system and method for avoiding voltage emergencies
Brandon Reagen, Gu Wei, and David Brooks. 2015. “How Hardware Accelerators Trade-Off Pipelining and Parallelism to Maximize Efficiency.” In Boston Area Architecture Workshop (BARC). Publisher's Version
Yakun Shao, Sam Xi, Viji Srinivasan, Gu Wei, and David Brooks. 2015. “Toward Cache-Friendly Hardware Accelerators.” In HPCA Sensors and Cloud Architectures Workshop (SCAW). Publisher's VersionAbstract
Increasing demand for power-efficient, high-performance computing has spurred a growing number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as servers and desktops. Despite their energy efficiency, fixed-function accelerators lack programmability, especially compared with general-purpose processors. Today’s accelerators rely on software-managed scratchpad memory and Direct Memory Access (DMA) to provide fixed-latency memory access and data transfer, which leads to significant chip resource and software engineering costs. On the other hand, hardware-managed caches with support for virtual memory and cache coherence are well-known to ease programmability in general-purpose processors, but these features are not commonly supported in today’s fixed-function accelerators. As a first step toward cache-friendly accelerator design, this paper discusses limitations of scratchpad-based memories in today’s accelerators, identifies challenges to support hardware-managed caches, and explores opportunities to ease the cache integration.
Toward Cache-Friendly Hardware Accelerators
Khalid Al-Hawaj, Simone Campanoni, Gu Wei, and David Brooks. 2015. “Unified Cache: A Case for Low-Latency Communication.” In 3rd International Workshop on Parallelism in Mobile Platforms (PRISM). Portland, OR, USA.Abstract
Increasing computational demand on mobile devices calls for energy-friendly solutions for accelerating single programs. In the multicore era, thread level parallelism (TLP) can accelerate single-threaded programs without requiring power-hungry cores. HELIX-RC, a recently proposed co-design between the HELIX parallelizing compiler and its target architecture, shows that substantial TLP can be extracted from loops with small bodies by optimizing core-to-core communication. Previously, the effectiveness of the HELIX-RC approach has been demonstrated through simulation. In this paper, we evaluate a HELIXRC-like solution on a real platform. We have developed a simplified version of the HELIX-RC architecture that we call unified cache, and we have implemented it on an FPGA board. Our design augments a multicore platform with a simplified ring cache—the architectural component of the HELIX-RC co-design. With the aid of microbenchmarks, our FPGA prototype confirms the HELIX-RC findings. David Brooks After describing both the ring cache and the parallel code generated by the HELIX compiler, we sketch the design of the unified cache and we evaluate its implementation on a Xilinx VC707 FPGA board.
Unified Cache: A Case for Low-Latency Communication
2014
Brandon Reagen, Robert Adolf, Sophia Shao, Gu Wei, and David Brooks. 10/26/2014. “MachSuite: Benchmarks for Accelerator Design and Customized Architectures.” In IEEE International Symposium on Workload Characterization (IISWC). Publisher's VersionAbstract
Recent high-level synthesis and accelerator-related architecture papers show a great disparity in workload selection among projects and research groups. To provide standardization within the accelerator research community, we present MachSuite, a benchmark suite for high-level synthesis tools and accelerator-centric architectures. MachSuite is the compilation of carefully selected workloads to cover a diverse application space and algorithm choices. All the benchmarks in MachSuite are implemented to be well suited for high-level synthesis. A thorough characterization further demonstrates the diverse behaviors among benchmarks, representative of different customization challenges. MachSuite enables commensurability across research projects while mitigating the burden of accelerator implementation and workload selection.
MachSuite: Benchmarks for Accelerator Design and Customized Architectures
Svilen Kanev, Kim Hazelwood, Gu Wei, and David Brooks. 10/26/2014. “Tradeoffs between Power Management and Tail Latency in Warehouse-Scale Applications.” In International Symposium on Workload Characterization (IISWC), Pp. 31-40. IEEE. Publisher's VersionAbstract
The growth in datacenter computing has increased the importance of energy-efficiency in servers. Techniques to reduce power have brought server designs close to achieving energy-proportional computing. However, they stress the inherent tradeoff between aggressive power management and quality of service (QoS) – the dominant metric of performance in datacenters. In this paper, we characterize this tradeoff for 15 benchmarks representing workloads from Google’s datacenters. We show that 9 of these benchmarks often toggle their cores between short bursts of activity and sleep. In doing so, they stress sleep selection algorithms and can cause tail latency degradation or missed potential for power savings of up to 10% on important workloads like web search. However, improving sleep selection alone is not sufficient for large efficiency gains on current server hardware. To guide the direction needed for such large gains, we profile datacenter applications for susceptibility to dynamic voltage and frequency scaling (DVFS). We find the largest potential in DVFS which is cognizant of latency/power tradeoffs on a workload-per-workload basis.
Tradeoffs between Power Management and Tail Latency in Warehouse-Scale Applications
Svilen Kanev, Kim Hazelwood, Gu Wei, and David Brooks. 10/26/2014. “Tradeoffs between power management and tail latency in warehouse-scale applications.” In 2014 IEEE International Symposium on Workload Characterization (IISWC), Pp. 31–40. IEEE. Publisher's VersionAbstract
The growth in datacenter computing has increased the importance of energy-efficiency in servers. Techniques to reduce power have brought server designs close to achieving energy-proportional computing. However, they stress the inherent tradeoff between aggressive power management and quality of service (QoS) - the dominant metric of performance in datacenters. In this paper, we characterize this tradeoff for 15 benchmarks representing workloads from Google's datacenters. We show that 9 of these benchmarks often toggle their cores between short bursts of activity and sleep. In doing so, they stress sleep selection algorithms and can cause tail latency degradation or missed potential for power savings of up to 10% on important workloads like web search. However, improving sleep selection alone is not sufficient for large efficiency gains on current server hardware. To guide the direction needed for such large gains, we profile datacenter applications for susceptibility to dynamic voltage and frequency scaling (DVFS). We find the largest potential in DVFS which is cognizant of latency/power tradeoffs on a workload-per-workload basis.
Tradeoffs between Power Management and Tail Latency in Warehouse-Scale Applications
Michael Lyons, Gu Wei, and David Brooks. 10/19/2014. “Multi-accelerator system development with the shrinkfit acceleration framework.” In 2014 IEEE 32nd International Conference on Computer Design (ICCD), Pp. 75–82. IEEE. Publisher's VersionAbstract
This paper introduces the ShrinkFit accelerator framework, which simplifies the design of systems combining multiple accelerators. A single ShrinkFit system design can be deployed to FPGAs large and small, without time-consuming architectural parameter surveys. We describe four ShrinkFit accelerators implemented for an FPGA-based robotic bee brain prototype and demonstrate the flexibility of ShrinkFit with low performance overheads (under 10% on average) and low resource overheads (0-8% for accelerators and under 2% for hard logic blocks).
Multi-accelerator system development with the ShrinkFit acceleration framework
Michael Lyons, Gu Wei, and David Brooks. 10/2014. “Multi-accelerator system development with the ShrinkFit acceleration framework.” In International Conference on Computer Design. Seoul, Korea (South). Publisher's VersionAbstract
This paper introduces the ShrinkFit accelerator framework, which simplifies the design of systems combining multiple accelerators. A single ShrinkFit system design can be deployed to FPGAs large and small, without time-consuming architectural parameter surveys. We describe four ShrinkFit accelerators implemented for an FPGA-based robotic bee brain prototype and demonstrate the flexibility of ShrinkFit with low performance overheads (under 10% on average) and low resource overheads (0-8% for accelerators and under 2% for hard logic blocks).
Multi-accelerator system development with the ShrinkFit acceleration framework
Yakun Shao, Brandon Reagen, Gu Wei, and David Brooks. 6/14/2014. “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures.” In International Symposium on Computer Architecture (ISCA). Publisher's VersionAbstract
Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.
Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures
Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy Jones, Gu Wei, and David Brooks. 6/14/2014. “HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs.” In International Symposium on Computer Architecture (ISCA), 3rd ed., 42: Pp. 217–228. Publisher's VersionAbstract
Data dependences in sequential programs limit paralleliza- tion because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.
HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
Lin Shiung and Gu Wei. 6/10/2014. “Voltage regulator integrated with semiconductor chip.” United States of America US8749021B2 (U.S Patent). Publisher's VersionAbstract
The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.
Voltage regulator integrated with semiconductor chip
Pradip Bose, David Brooks, Subhasish Mitra, Karthick Rajamani, Mircea Stan, Kevin Skadron, and Gu Wei. 4/1/2014. “Cross-Layer Modeling Framework for Energy-Efficient Resilience”. Publisher's VersionAbstract

We describe a novel cross-layer, resilience focused integrated modeling framework. This is targeted to help define ultra energy-efficient embedded systems in the post-14nm CMOS design era, without compromising system-level resilience. The targeted application domain is represented by the suite of applications and kernels announced as part of the ongoing PERFECT program sponsored by DARPA MTO.

Cross-Layer Modeling Framework for Energy-Efficient Resilience
Xuan Zhang, Tao Tong, David Brooks, and Gu Wei. 3/31/2014. “Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip.” In IEEE Transactions on Circuits and Systems (TCAS). Vol. PP. Publisher's VersionAbstract
A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme that can tolerate supply noise and improve performance when implemented with an integrated voltage regulator (IVR). Measurements from a `brain' SoC, implemented in 40 nm CMOS, demonstrate 2 × performance improvement with adaptive-frequency clocking over conventional fixed-frequency clocking. Combining adaptive-frequency clocking with open-loop IVR extends error-free operation to a wider battery voltage range (2.8 to 3.8 V) with higher average performance.
Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip
Simone Campanoni, Svilen Kanev, Kevin Brownell, Gu Wei, and David Brooks. 2014. “Breaking Cyclic-Multithreading Parallelization with XML Parsing.” In International Workshop on Parallelism in Mobile Platforms (PRISM). Publisher's VersionAbstract
HELIX-RC, a modern re-evaluation of the cyclic-multithreading (CMT) compiler technique, extracts threads from sequential code automatically. As a CMT approach, HELIX-RC gains performance by running iterations of the same loop on different cores in a multicore. It successfully boosts performance for several SPEC CINT benchmarks previously considered unparallelizable. However, this paper shows there are workloads with different characteristics, which even idealized CMT cannot parallelize. We identify how to overcome an inherent limitation of CMT for these workloads. CMT techniques only run iterations of a single loop in parallel at any given time. We propose exploiting parallelism not only within a single loop, but also among multiple loops. We call this execution model Multiple CMT (MCMT), and show that it is crucial for auto-parallelizing a broader class of workloads. To highlight the need for MCMT, we target a workload that is naturally hard for CMT – parsing XML-structured data. We show that even idealized CMT fails on XML parsing. Instead, MCMT extracts speedups up to 3.9x on 4 cores.
Breaking Cyclic-Multithreading Parallelization with XML Parsing
2013
Xuan Zhang, David Brooks, and Gu Wei. 11/11/2013. “A 20uW 10MHz Relaxation Oscillator with Adaptive Bias and Fast Self-Calibration in 40nm CMOS for Micro-Aerial Robotics Application.” In IEEE Asian Solid-State Circuits Conference (ASSCC). Publisher's VersionAbstract
Efficient actuation control of flapping-wing microrobots requires a low-power frequency reference with good absolute accuracy. To meet this requirement, we designed a fully-integrated 10MHz relaxation oscillator in a 40nm CMOS process. By adaptively biasing the continuous-time comparator, we are able to achieve a power consumption of 20μW, a 68% reduction to the conventional fixed bias design. A built-in self-calibration controller enables fast post-fabrication calibration of the clock frequency. Measurements show a frequency drift of 1.2% as the battery voltage changes from 3V to 4.1V.
A 20uW 10MHz Relaxation Oscillator with Adaptive Bias and Fast Self-Calibration in 40nm CMOS for Micro-Aerial Robotics Application

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