Evaluation of voltage stacking for near-threshold multicore computing


Sae Lee, David Brooks, and Gu Wei. 7/2012. “Evaluation of voltage stacking for near-threshold multicore computing.” In ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Pp. 373–378https. Publisher's Version


This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each other, voltage stacking reduces the chip current draw and simplifies off-chip power delivery but within-die voltage noise due to inter-layer current mismatch is an issue. Results show that unlike conventional power delivery schemes, supply rail impedance in voltage stacked systems depend on aggregate power consumption, leading to better noise immunity for high power (low impedance) operation for many-core processors.

Last updated on 04/27/2022