Publications by Year: 2003

Gu Wei, Stonick T, Weinlader Dan, Sonntag Jeff, and Searles Shawn. 12/13/2003. “A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS.” In 2003 IEEE International Solid-State Circuits Conference, 12/13/2003. Digest of Technical Papers. ISSCC., Pp. 464–465. IEEE. Publisher's VersionAbstract
Low-jitter clock generation is a critical component for enabling robust high-speed operation of 5Gb/s backplane transceivers. The implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying delay-locked loop (MDLL) is described. The choice depends on the noise characteristics of the input clock source. This MP/DLL design is implemented in a 0.25/spl mu/m CMOS process and operates with a 2.5V supply.
David Brooks, Pradip Bose, Vijayalakshmi Srinivasan, Michael Gschwind, Philip Emma, and Michael Rosenfield. 9/2003. “New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.” IBM Journal of Research and Development, 47, 5.6, Pp. 653–670. Publisher's VersionAbstract
The PowerTimer toolset has been developed for use in early-stage, microarchitecture-level power-performance analysis of microprocessors. The key component of the toolset is a parameterized set of energy functions that can be used in conjunction with any given cycle-accurate microarchitectural simulator. The energy functions model the power consumption of primitive and hierarchically composed building blocks which are used in microarchitecture-level performance models. Examples of structures modeled are pipeline stage latches, queues, buffers and component read/write multiplexers, local clock buffers, register files, and cache array macros. The energy functions can be derived using purely analytical equations that are driven by organizational, circuit, and technology parameters or behavioral equations that are derived from empirical, circuit-level simulation experiments. After describing the modeling methodology, we present analysis results in the context of a current-generation superscalar processor simulator to illustrate the use and effectiveness of such early-stage models. In addition to average power and performance tradeoff analysis, PowerTimer is useful in assessing the typical and worst-case power (or current) swings that occur between successive cycle windows in a given workload execution. Such a characterization of workloads at the early stage of microarchitecture definition helps pinpoint potential inductive noise problems on the voltage rail that can be addressed by designing an appropriate package or by suitably tuning the dynamic power management controls within the processor.
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
Stonick T, Gu Wei, Sonntag L, and Weinlader K. 5/15/2003. “An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS.” IEEE Journal of Solid-State Circuits, 38, 3, Pp. 436–443. Publisher's VersionAbstract
This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm/sup 2/ device is implemented in a 0.25 /spl mu/m CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS
P Bose, David Brooks, A Buyuktosunoglu, P. Cook, K Das, P Emma, M Gschwind, H Jacobson, T Karkhanis, and P Kudva. 4/1/2003. “Early-stage definition of LPX: A low power issue-execute processor.” Power-Aware Computer Systems, Pp. 89–92. Publisher's VersionAbstract

We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a vector (SIMD) multimedia extension. The objective of this project is to validate some key new ideas in power-aware microarchitecture techniques, supported by recent advances in circuit design and clocking.

Early-stage definition of LPX: A low power issue-execute processor
Russ Joseph, David Brooks, and Margaret Martonosi. 2/12/2003. “Control techniques to eliminate voltage emergencies in high performance processors.” In High-Performance Computer Architecture, 2/12/2003. HPCA-9 2/12/2003. Proceedings. The Ninth International Symposium on, Pp. 79–90. Anaheim, CA, USA: IEEE. Publisher's VersionAbstract
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effective at reducing average power, many of these techniques have the undesired side-effect of increasing both the variability of power dissipation and the variability of current drawn by the processor This increase in current variability, often referred to as the dI/dt problem, can cause supply voltage fluctuations. Such voltage fluctuations lead to unreliable circuits if not addressed, and increasingly expensive chip packaging techniques are needed to mitigate them. This paper proposes and evaluates a methodology for augmenting packaging techniques for dI/dt with microarchitectural control mechanisms. We discuss the resonant frequencies most relevant to current microprocessor packages, produce and evaluate a "dI/dt stressmark" that exercises the system at its resonant frequency, and characterize the behavior of more mainstream applications. Based on these results plus evaluations of the impact of controller error and delay, our microarchitectural control proposals offer bounds on supply voltage fluctuations, with nearly negligible impact on performance and energy. With the ITRS roadmap predicting aggressive drops in supply voltage and power supply impedances in coming chip generations, novel voltage control techniques will be required to stay on track. Our microarchitectural dI/dt controllers represent a step in this direction.
Control techniques to eliminate voltage emergencies in high performance processors
Hanumolu Kumar, Bryan Casper, Mooney Randy, Gu Wei, and Moon Ku. 2003. “Analysis of PLL clock jitter in high-speed serial links.” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50, 11, Pp. 879–886.
Jaeha Kim, A Horowitz, and Gu Wei. 2003. “Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach.” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50, 11, Pp. 860–869.