A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS
Publication information:
Gu Wei, Stonick T, Weinlader Dan, Sonntag Jeff, and Searles Shawn. 2003. “A 500MHz MP DLL Clock Generator for a 5Gb S Backplane Transceiver in 0.25 Spl Mu M CMOS”. In 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., Pp. 464–465. IEEE
Abstract
Low-jitter clock generation is a critical component for enabling robust high-speed operation of 5Gb/s backplane transceivers. The implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying delay-locked loop (MDLL) is described. The choice depends on the noise characteristics of the input clock source. This MP/DLL design is implemented in a 0.25/spl mu/m CMOS process and operates with a 2.5V supply.