With Moore's law ending, there is a major push towards heterogeneity, where the modern SoCs consist of general-purpose CPUs, specialized hardware accelerators, GPUs, and FPGAs. This trend is especially prevalent for AI and internet of things (IoT) applications, such as the recent computer vision chips for autonomous driving as well as ultra-low-power SoCs for wearable electronics. Our group has developed infrastructure to allow for rapid design space exploration of heterogeneous SoCs targeting AI applications.

While our Aladdin tool can accurately model a variety of accelerator designs at pre-RTL level, its integration with gem5 (i.e., gem5-Aladdin) models and simulates complex SoCs consisting of CPUs, accelerators, NoC, and memory hierarchies. Recently, our SMAUG framework, building on gem5-Aladdin, supports modeling of deep neural network accelerators and can simulate a variety of commonly-used DNN and RNN models as well as hardware architectures for these accelerators such as SIMD and systolic arrays. In addition, we have also introduced ParaDNN tool that can generate thousands of parameterized multi-layer NN models, which can then be used to benchmark different computing platforms such as Google TPU, Nvidia GPU etc. Finally, for a fast and scalable automated DSE, we also use Bayesian optimization in conjunction with the above modeling frameworks to allow for efficient black-box optimizations of heterogeneous SoCs.