Emerging Embedded Non-Volatile Memory (eNVM) Technologies
In the face of the memory wall, DRAM technology scaling issues, and ever-increasing application data demands across computing systems from the edge to the cloud, the exploration and evaluation of emerging, alternative memory technologies is an essential pursuit for enabling efficient future memory systems. We investigate, model, and evaluate the system-level implications of memory technology proposals in varying stages of development, including RRAM, STT-RAM, PCRAM, and Ferroelectric RAM. The unique physical properties of alternative, embeddable memory technologies necessitate careful co-design among memory cell characteristics, architecture design choices, and application-level optimizations. Thus, we develop and adopt a full-stack approach to modeling and evaluating systems that leverage eNVM technologies, including application-level fault tolerance analysis and analytical performance, power, and area evaluation frameworks.
Additionally, we have successfully fabricated and measured the multi-level-cell programming capabilities of Charge Trap Transistors (CTTs) as an incredibly dense and entirely CMOS-compatible eNVM. Our ongoing work investigates both the design, integration, and fabrication of SoCs leveraging eNVMs and the development of comprehensive tools to facilitate design space exploration and determine the viability of eNVM proposals in different system and application contexts.