Heterogeneous System Modeling and Optimization

heterogeneous sys modeling optimizations

With Moore's law ending, there is a major push towards heterogeneity, where the modern SoCs consist of general-purpose CPUs, specialized hardware accelerators, GPUs, and FPGAs. This trend is especially prevalent for AI and internet of things (IoT) applications, such as the recent computer vision chips for autonomous driving as well as ultra-low-power SoCs for wearable electronics. Our group has developed infrastructure to allow for rapid design space exploration of heterogeneous SoCs targeting AI applications.

While our Aladdin tool can accurately model a variety of accelerator designs at pre-RTL level, its integration with gem5 (i.e., gem5-Aladdin) models and simulates complex SoCs consisting of CPUs, accelerators, NoC, and memory hierarchies. Recently, our SMAUG framework, building on gem5-Aladdin, supports modeling of deep neural network accelerators and can simulate a variety of commonly-used DNN and RNN models as well as hardware architectures for these accelerators such as SIMD and systolic arrays. In addition, we have also introduced ParaDNN tool that can generate thousands of parameterized multi-layer NN models, which can then be used to benchmark different computing platforms such as Google TPU, Nvidia GPU etc. Finally, for a fast and scalable automated DSE, we also use Bayesian optimization in conjunction with the above modeling frameworks to allow for efficient black-box optimizations of heterogeneous SoCs.

Select Publications

2022

Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, and Sharad Malik. 2022. “Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs With a Formal Software Hardware Interface
Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, and Sharad Malik. 2022. “Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs With a Formal Software Hardware Interface
Abdulrahman Mahmoud, Thierry Tambe, Tarek Aloui, David Brooks, and Gu-Yeon Wei. 2022. “GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators
Abdulrahman Mahmoud, Thierry Tambe, Tarek Aloui, David Brooks, and Gu-Yeon Wei. 2022. “GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators

2021

Bo-Yuan Huang, Steven Lyubomirsky, Thierry Tambe, Yi Li, Mike He, Gus Smith, Gu-Yeon Wei, Aarti Gupta, Sharad Malik, and Zachary Tatlock. 2021. “From DSLs to Accelerator-Rich Platform Implementations: Addressing the Mapping Gap”. Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’21)
Bo-Yuan Huang, Steven Lyubomirsky, Thierry Tambe, Yi Li, Mike He, Gus Smith, Gu-Yeon Wei, Aarti Gupta, Sharad Malik, and Zachary Tatlock. 2021. “From DSLs to Accelerator-Rich Platform Implementations: Addressing the Mapping Gap”. Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’21)

2017

Brandon Reagen, Jose Hernandez-Lobato, Robert Adolf, Michael Gelbart, Paul Whatmough, Gu Wei, and David Brooks. 2017. “A Case for Efficient Accelerator Design Space Exploration via Bayesian Optimization”. In International Symposium on Low Power Electronics and Design. Taipei, Taiwan
Brandon Reagen, Jose Hernandez-Lobato, Robert Adolf, Michael Gelbart, Paul Whatmough, Gu Wei, and David Brooks. 2017. “A Case for Efficient Accelerator Design Space Exploration via Bayesian Optimization”. In International Symposium on Low Power Electronics and Design. Taipei, Taiwan

2016

Yakun Shao, Sam Xi, Vijayalakshmi Srinivasan, Gu Wei, and David Brooks. 2016. “Co-Designing Accelerators and SoC Interfaces Using Gem5-Aladdin”. In International Symposium on Microarchitecture (MICRO). Taipei, Taiwan
Yakun Shao, Sam Xi, Vijayalakshmi Srinivasan, Gu Wei, and David Brooks. 2016. “Co-Designing Accelerators and SoC Interfaces Using Gem5-Aladdin”. In International Symposium on Microarchitecture (MICRO). Taipei, Taiwan

2014

Yakun Shao, Brandon Reagen, Gu Wei, and David Brooks. 2014. “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures”. In International Symposium on Computer Architecture (ISCA)
Yakun Shao, Brandon Reagen, Gu Wei, and David Brooks. 2014. “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures”. In International Symposium on Computer Architecture (ISCA)