“Agile” Chip Building (CRAFT, ChipKit, Chip Gallery)

Agile and Rapid Design of Research Test Chips

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Research test chips are the ultimate experiment to demonstrate the true value of novel computer architecture innovations. They are always very highly regarded by reviewers as the most honest evaluation of a new hardware proposal. In addition, there is a huge pedagogical value in taping out test chips, as it offers insight on the impact of real hardware and microarchitecture details that are critical in guiding higher level architecture decisions and trade-offs. Nonetheless, despite all this, taping out test chips remains a challenge for those who are following this path for the first time. Traditionally, research chips have been time-consuming to design, fabricate and test, and often error prone - potentially requiring re-spins to fix problems.

To help lower the entry barrier for chip tape-outs, we have pioneered an open-source framework, CHIPKIT, centered on agile and reusable themes. Emphasizing reuse greatly reduces development cost and at the same time minimizes the opportunity for silicon bugs, freeing the designer to focus on differentiating features. While agile design seeks to follow a methodology where changes can be readily implemented late into the design cycle, without significant disruption or risk. A full-chip validation methodology, covering the entire design flow, is then adapted onto this system-on-chip scaffold in order to ensure functional correctness. Following the CHIPKIT framework has allowed steady and new tape-outs (a subset illustrated in the gallery below) to be developed with very low-risk, high success rate, and with design and verification efforts reduced by orders of magnitude.


 

Select Publications

2022

Thierry Tambe, David Brooks, and Gu-Yeon Wei. 2022. “Learnings from a HLS-Based High-Productivity Digital VLSI Flow”. In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22)
Thierry Tambe, David Brooks, and Gu-Yeon Wei. 2022. “Learnings from a HLS-Based High-Productivity Digital VLSI Flow”. In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22)

2020

Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Tambe Thierry, Rob Rutenbar, Gu Wei, and Gu Wei. 2020. “A Scalable Bayesian Inference Accelerator for Unsupervised Learning”. In IEEE Hot Chips 31 Symposium. Palo Alto, CA, USA
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Tambe Thierry, Rob Rutenbar, Gu Wei, and Gu Wei. 2020. “A Scalable Bayesian Inference Accelerator for Unsupervised Learning”. In IEEE Hot Chips 31 Symposium. Palo Alto, CA, USA
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Thierry Tambe, Rob Rutenbar, David Brooks, and Gu-Yeon Wei. 2020. “A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception Using Parallel Gibbs Sampling in 16nm”. In IEEE Symposium on VLSI Circuits (VLSI)
Glenn Ko, Yuji Chai, Marco Donato, Paul Whatmough, Thierry Tambe, Rob Rutenbar, David Brooks, and Gu-Yeon Wei. 2020. “A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception Using Parallel Gibbs Sampling in 16nm”. In IEEE Symposium on VLSI Circuits (VLSI)

2019

Sae Lee, Paul Whatmough, David Brooks, and Gu Wei. 2019. “A 16-Nm Always-on DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs”. IEEE Journal of Solid-State Circuits, 54, 7, Pp. 1982-92
Sae Lee, Paul Whatmough, David Brooks, and Gu Wei. 2019. “A 16-Nm Always-on DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs”. IEEE Journal of Solid-State Circuits, 54, 7, Pp. 1982-92
Paul Whatmough, Sae Lee, Marco Donato, Hsea Hsueh, Sam Xi, Udit Gupta, Lillian Pentecost, Glenn Ko, David Brooks, and Gu Wei. 2019. “A 16nm 25mm2 SoC With a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to EFPGA and Cache-Coherent Accelerators”. Symposium on VLSI Circuits
Paul Whatmough, Sae Lee, Marco Donato, Hsea Hsueh, Sam Xi, Udit Gupta, Lillian Pentecost, Glenn Ko, David Brooks, and Gu Wei. 2019. “A 16nm 25mm2 SoC With a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to EFPGA and Cache-Coherent Accelerators”. Symposium on VLSI Circuits

2018

Sae Lee, Paul Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks, and Gu Wei. 2018. “A Wide Dynamic Range Sparse FC-DNN Processor With Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET”. ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference
Sae Lee, Paul Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks, and Gu Wei. 2018. “A Wide Dynamic Range Sparse FC-DNN Processor With Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET”. ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference