Energy-efficient design of high-speed links


Gu Wei, Horowitz Mark, and Jaeka Kim. 2002. “Energy-efficient design of high-speed links.” In Power Aware Design Methodologies, 8: Pp. 201–239. Springer, Boston, MA. Publisher's Version


Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and describes some of the power vs. performance trade-offs associated with various design choices. The chapter then investigates various techniques that a designer may employ to reduce power consumption. Three examples of link designs and link building blocks found in the literature present energy-efficient implementations of these techniques.

Last updated on 05/06/2022