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306 results
2003
Bose, David Brooks, Buyuktosunoglu, P. Cook, Das, Emma, Gschwind, Jacobson, Karkhanis, and Kudva. 2003. “Early-Stage Definition of LPX: A Low Power Issue-Execute Processor”. Power-Aware Computer Systems, Pp. 89–92
Bose, David Brooks, Buyuktosunoglu, P. Cook, Das, Emma, Gschwind, Jacobson, Karkhanis, and Kudva. 2003. “Early-Stage Definition of LPX: A Low Power Issue-Execute Processor”. Power-Aware Computer Systems, Pp. 89–92
We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a...
Stonick T, Gu Wei, Sonntag L, and Weinlader K. 2003. “An Adaptive PAM-4 5-Gb S Backplane Transceiver in 0.25- Spl Mu M CMOS”. IEEE Journal of Solid-State Circuits, 38, 3, Pp. 436–443
Stonick T, Gu Wei, Sonntag L, and Weinlader K. 2003. “An Adaptive PAM-4 5-Gb S Backplane Transceiver in 0.25- Spl Mu M CMOS”. IEEE Journal of Solid-State Circuits, 38, 3, Pp. 436–443
This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total...
Jaeha Kim, Horowitz, and Gu Wei. 2003. “Design of CMOS Adaptive-Bandwidth PLL DLLs: A General Approach”. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50, 11, Pp. 860–869
Jaeha Kim, Horowitz, and Gu Wei. 2003. “Design of CMOS Adaptive-Bandwidth PLL DLLs: A General Approach”. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50, 11, Pp. 860–869
Hanumolu Kumar, Bryan Casper, Mooney Randy, Gu Wei, and Moon Ku. 2003. “Analysis of PLL Clock Jitter in High-Speed Serial Links”. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50, 11, Pp. 879–886
Hanumolu Kumar, Bryan Casper, Mooney Randy, Gu Wei, and Moon Ku. 2003. “Analysis of PLL Clock Jitter in High-Speed Serial Links”. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50, 11, Pp. 879–886
Gu Wei, Stonick T, Weinlader Dan, Sonntag Jeff, and Searles Shawn. 2003. “A 500MHz MP DLL Clock Generator for a 5Gb S Backplane Transceiver in 0.25 Spl Mu M CMOS”. In 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., Pp. 464–465. IEEE
Gu Wei, Stonick T, Weinlader Dan, Sonntag Jeff, and Searles Shawn. 2003. “A 500MHz MP DLL Clock Generator for a 5Gb S Backplane Transceiver in 0.25 Spl Mu M CMOS”. In 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., Pp. 464–465. IEEE
Low-jitter clock generation is a critical component for enabling robust high-speed operation of 5Gb/s backplane transceivers. The implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying...
2002
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip Strenski, and Philip Emma. 2002. “Optimizing Pipelines for Power and Performance”. In Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE ACM International Symposium on, Pp. 333–344. IEEE
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip Strenski, and Philip Emma. 2002. “Optimizing Pipelines for Power and Performance”. In Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE ACM International Symposium on, Pp. 333–344. IEEE
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage...
Alper Buyuktosunoglu, David Albonesi, Stanley Schuster, David Brooks, Pradip Bose, and Peter Cook. 2002. “Power-Efficient Issue Queue Design”. In Power Aware Computing, Pp. 35–58. Kluwer Academic Publishers
Alper Buyuktosunoglu, David Albonesi, Stanley Schuster, David Brooks, Pradip Bose, and Peter Cook. 2002. “Power-Efficient Issue Queue Design”. In Power Aware Computing, Pp. 35–58. Kluwer Academic Publishers
Increasing levels of power dissipation threaten to limit the performance gains of future high-end, out-of-order issue microprocessors. Therefore, it is imperative that designers devise techniques that significantly reduce the power dissipation of the key...
Martonosi, David Brooks, and Tiwari. 2002. “Architecture-Level Power Modeling With Wattch”. Computer, 35, 2, Pp. 64–64
Martonosi, David Brooks, and Tiwari. 2002. “Architecture-Level Power Modeling With Wattch”. Computer, 35, 2, Pp. 64–64
Pradip Bose, David Brooks, Viji Srinivasan, and Philip Emma. 2002. Power-Performance and Power Swing Characterization in Adaptive Microarchitectures. Technical Paper Archive - Research Reports. IBM Research
Pradip Bose, David Brooks, Viji Srinivasan, and Philip Emma. 2002. Power-Performance and Power Swing Characterization in Adaptive Microarchitectures. Technical Paper Archive - Research Reports. IBM Research
In this paper, we present an analysis of some of the fundamental power-performance tradeoffs in processors that employ adaptive techniques to vary sizes, bandwidths, clock-gating modes and clock frequencies. Initial expectations are set using simple...
Gu Wei, Horowitz Mark, and Jaeka Kim. 2002. “Energy-Efficient Design of High-Speed Links”. In Power Aware Design Methodologies, 8:Pp. 201–239. Springer, Boston, MA
Gu Wei, Horowitz Mark, and Jaeka Kim. 2002. “Energy-Efficient Design of High-Speed Links”. In Power Aware Design Methodologies, 8:Pp. 201–239. Springer, Boston, MA
Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and...
2001
David Brooks and Margaret Martonosi. 2001. “Dynamic Thermal Management for High-Performance Microprocessors”. In High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on, Pp. 171–182. IEEE
David Brooks and Margaret Martonosi. 2001. “Dynamic Thermal Management for High-Performance Microprocessors”. In High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on, Pp. 171–182. IEEE
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance...
Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, and David Albonesi. 2001. “An Adaptive Issue Queue for Reduced Power at High Performance”. Power-Aware Computer Systems, Pp. 25–39
Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, and David Albonesi. 2001. “An Adaptive Issue Queue for Reduced Power at High Performance”. Power-Aware Computer Systems, Pp. 25–39
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate...