Evaluating techniques for exploiting instruction slack


Yau Chin, John Sheu, and David Brooks. 10/11/2004. “Evaluating techniques for exploiting instruction slack.” In Computer Design: VLSI in Computers and Processors, 10/11/2004. ICCD 10/11/2004. Proceedings. IEEE International Conference on, Pp. 375–378. San Jose, CA, USA: IEEE. Publisher's Version


In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efficient, longer latency pipelines or provide dynamically scaled pipelines using multiple clock domains. Issuing instructions with slack to slower pipelines can result in substantial power savings, with minimal performance loss. Considering both dynamic and static power dissipation, we found that by using longer latency pipelines the power of functional unit pipelines decreases by 20% to 55% with a performance impact of 0% to 3% for SPEC2000 and MediaBench workloads. Dynamic scaling reduces the performance loss in intense multimedia workloads by up to 2%, but achieves lower power savings.
Last updated on 05/04/2022