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Emerging Embedded Non-Volatile Memory (eNVM) Technologies In the face of the memory wall, DRAM technology scaling issues, and ever-increasing application data demands across computing systems from the edge to the cloud, the exploration and evaluation of...

A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM

Journal Article

We propose a new algorithm for training neural networks with binary activations and multi-level weights, which enables efficient processing-in-memory circuits with embedded nonvolatile memories (eNVM). Binary activations obviate costly DACs and ADCs...

On-Chip Deep Neural Network Storage with Multi-Level eNVM

Conference Paper

One of the biggest performance bottlenecks of today’s neural network (NN) accelerators is off-chip memory accesses. In this paper, we propose a method to use multi-level, embedded non-volatile memory (eNVM) to eliminate all off-chip weight accesses. The...

On-chip deep neural network storage with multi-level eNVM

Conference Paper

One of the biggest performance bottlenecks of today's neural network (NN) accelerators is off-chip memory accesses [11]. In this paper, we propose a method to use multi-level, embedded nonvolatile memory (eNVM) to eliminate all off-chip weight accesses...

MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge

Journal Article

The combination of specialized hardware and embedded nonvolatile memories (eNVM) holds promise for energy-efficient deep neural network (DNN) inference at the edge. However, integrating DNN hardware accelerators with eNVMs still presents several...

MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation

Conference Paper

Deeply embedded applications require low-power, low-cost hardware that fits within stringent area constraints. Deep learning has many potential uses in these domains, but introduces significant inefficiencies stemming from off-chip DRAM accesses of model...

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

Conference Paper

Repeated off-chip memory accesses to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy...

On-Chip Deep Neural Network Storage with Multi-Level eNVM

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On-chip deep neural network storage with multi-level eNVM

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A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM

Resource

EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference

Journal Article

Transformer-based language models such as BERT provide significant accuracy improvement for a multitude of natural language processing (NLP) tasks. However, their hefty computational and memory demands make them challenging to deploy to resource...

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