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Software

We have developed a great deal of software infrastructure to enable and assist our research. Links to project details and source code are found here.

gem5-Aladdin

gem5-Aladdin is an integration of the Aladdin accelerator simulator with the gem5 system simulator to enable simulation of end-to-end accelerated workloads on SoCs. You may download the code here. It is maintained by Sam Xi and Yakun Sophia Shao.

Fathom

Fathom is a collection of workloads for benchmarking modern machine learning techniques. Source code is available on GitHub. Fathom is maintained by Robert Adolf and Saketh Rama.

XIOSim

XIOSim is our x86 performance simulator. The code is available on GitHub. It is still actively developed and maintained by Svilen Kanev, Kevin Brownell, and Sam Xi, although updates are only pushed to GitHub for major releases.

Aladdin

Aladdin is our pre-RTL power and performance simulator for hardware accelerators. Please click here to download Aladdin.

MachSuite

MachSuite is a benchmark suite for high-level synthesis and accelerator-centric architectures. Please click here to download MachSuite.

WIICA

WIICA is the Workload ISA Independent Characterization for Applications tool. Please click here to download the tool.

ILDJIT

ILDJIT is our compilation framework using a high-level intermediate representation. The code is available on SourceForge. ILDJIT is maintained by Simone Campanoni.

LLVM-Tracer

LLVM-Tracer is an LLVM instrumentation pass to print out a dynamic LLVM IR execution trace, including dynamic values and memory addresses.

Please click here to download the tool.

McPAT CPU Models

We have developed McPAT power models for a recent high-performance multicore CPU. You may download these models here.

BayesSuite

BayesSuite is a collection of Bayesian inference workloads written in Stan framework. The code is available on GitHub. More details and profiling results on BayesSuite are in this paper. The repository is maintained by Emma Wang.

FlexASR

An AXI-programmable hardware accelerator for attention-based seq-to-seq networks. FlexASR can be configured to accelerate end-to-end RNN, GRU or LSTM models with attention mechanisms (e.g. Listen-Attend-and-Spell models). It was designed in Synthesizable SystemC followed by high-level synthesis (HLS) in order to generate RTL.. FlexASR code available on GitHub.

DeepRecSys

DeepRecSys provides an end-to-end infrastructure to study and optimize at-scale neural recommendation inference. The infrastructure is configurable across three main dimensions that represent different recommendation use cases: the load generator (query arrival patterns and size distributions), neural recommendation models, and underlying hardware platforms. DeepRecSys code available on GitHub.

EdgeBERT

EdgeBERT is a HW/SW co-design enabling sentence-level energy optimizations for latency-aware multi-task NLP inference. In this repo, we provide both the software and hardware modelings. EdgeBERT code available on GitHub.

RecPipe

RecPipe provides an end-to-end system to study and jointly optimize recommendation models and hardware for at-scale inference. This repository provides the RecPipe infrastructure which is configuration across different models and hardware (general purpose and specialized accelerator) dimensions. The infrastructure enables judicious comparison of recommendation quality, inference latency, and system-throughput. RecPipe code available on GitHub.

Smaug 

A deep learning framework that enables end-to-end simulation of DL models on custom SoCs with a variety of hardware accelerators. SMAUG is designed to enable DNN researchers to rapidly evaluate different accelerator and SoC designs and perform hardware-software co-design. Simulation is powered by the gem5-Aladdin SoC simulator, allowing users to easily write new hardware accelerators and integrate them into SMAUG for testing and exploration. Smaug code available on GitHub.

NVMExplorer

NVMExplorer is a cross-stack design space exploration framework for evaluating and comparing on-chip memory solutions including emerging, embedded non-volatile memories. NVMExplorer code available on GitHub.

gem5-Aladdin

gem5-Aladdin is an integration of the Aladdin accelerator simulator with the gem5 system simulator to enable simulation of end-to-end accelerated workloads on SoCs. You may download the code here. It is maintained by Sam Xi and Yakun Sophia Shao. gem5-Aladdin code available on GitHub.

Fathom

Fathom is a collection of workloads for benchmarking modern machine learning techniques. Fathom source code available on GitHub. Fathom is maintained by Robert Adolf and Saketh Rama.

XIOSim

XIOSim is our x86 performance simulator. XIOSim code available on GitHub. It is still actively developed and maintained by Svilen Kanev, Kevin Brownell, and Sam Xi, although updates are only pushed to GitHub for major releases.

Aladdin

Aladdin is our pre-RTL power and performance simulator for hardware accelerators. Aladdin code available on GitHub.

MachSuite

MachSuite is a benchmark suite for high-level synthesis and accelerator-centric architectures. Download MachSuite.

WIICA

WIICA is the Workload ISA Independent Characterization for Applications tool. Download WIICA.

ILDJIT

ILDJIT is our compilation framework using a high-level intermediate representation. ILDJIT code available on SourceForge. ILDJIT is maintained by Simone Campanoni.

LLVM-Tracer

LLVM-Tracer is an LLVM instrumentation pass to print out a dynamic LLVM IR execution trace, including dynamic values and memory addresses.
LLVM-Tracer code available on GitHub.

McPAT CPU Models

We have developed McPAT power models for a recent high-performance multicore CPU. Download McPAT power models.

BayesSuite

BayesSuite is a collection of Bayesian inference workloads written in Stan framework. BayesSuite code available on GitHub.
Paper with more details and profiling results on BayesSuite. The repository is maintained by Emma Wang.

Ares

Ares is a framework for quantifying the resilience of deep neural networks. Ares code available on GitHub.

CHAMPVis

CHAMPVis, Comparative Hierarchical Analysis of Microarchitectural Performance Visualization. CHAMPVis code available on GitHub.