Citation:
Hanumolu P, Wei Y, and U-K Moon. 6/15/2006. “A wide tracking range 0.2-4Gbps clock and data recovery circuit.” In 2006 Symposium on VLSI Circuits, 6/15/2006. Digest of Technical Papers., Pp. 71–72. IEEE. Publisher's Version
Abstract:
A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18mum CMOS process achieves BER < 10 -12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking