Replacing 6t srams with 3t1d drams in the l1 data cache to combat process variability
Publication information:
Xiaoyao Liang, Ramon Canal, Gu Wei, and David Brooks. 2008. “Replacing 6t Srams With 3t1d Drams in the L1 Data Cache to Combat Process Variability”. Micro, IEEE, 28, 1, Pp. 60–68
Abstract
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.