Process variation tolerant register files based on dynamic memories


Xiaoyao Liang, Ramon Canal, Gu Wei, and David Brooks. 12/2007. “Process variation tolerant register files based on dynamic memories.” In Workshop on Architectural Support for Gigascale Integration (ASGI-07) in conjunction with ISCA.


Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continued technology scaling. In this paper, we propose new on-chip memory architectures based on novel 3T1D DRAM (3-transistor, 1-diode dynamic memory) cells. We provide a detailed comparison between 6T and 3T1D designs in the context of a L1 data cache. The effects of physical device variation on a 3T1D cache can be lumped into variation of data retention times. This paper proposes a range of cache refresh and placement schemes that are sensitive to retention time, and we show that most of the retention time variations can be masked by the microarchitecture when using these schemes.Ω
Last updated on 05/02/2022