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Pipelined parallel architecture for high throughput MAP detectors

Citation:

Ruwan Ratnayake, Gu-Yeon Wei, and Aleksandar Kavcic. 6/2004. “Pipelined parallel architecture for high throughput MAP detectors.” In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), 2: Pp. II–505. IEEE. Publisher's Version
Pipelined parallel architecture for high throughput MAP detectors0 bytes

Abstract:

A maximum a posteriori probability (MAP) detector based on a forward only algorithm with high throughput is considered in this paper. MAP gives the optimal performance and, with Turbo decoding, can achieve performance close to the channel capacity limits. Deep pipelined architecture for the forward only method is presented and compared with the other throughput-increasing methods. Simulation results based on the iterative MAP-LDPC (low-density parity check) system are shown. Hardware implementation issues that exploit the regularities of the structure are also discussed.
Last updated on 05/04/2022