A mixed PLL/DLL architecture for low jitter clock generation


Yong Cheol Bae and Gu-Yeon Wei. 5/23/2004. “A mixed PLL/DLL architecture for low jitter clock generation.” In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), 4: Pp. IV–788. Vancouver, BC, Canada: IEEE. Publisher's Version


This paper presents a mixed PLL/DLL architecture for low-jitter clock generation that merges phase-locked loop (PLL) and delay-locked loop (DLL) characteristics. It relies on an interpolator to configure the loop to operate more like a PLL or more like a DLL depending on the interpolator's settings. The ability to vary interpolator settings enables wide range control of the clock generator's loop bandwidth. Therefore, the loop bandwidth can readily be adjusted to accommodate different noise conditions. A discrete-time Z-domain analysis is provided to illustrate the noise filtering characteristics of the loop in the presence of various noise sources and highlight the potential advantages of the mixed PLL/DLL architecture. Simulation results verify stable operation of the loop designed for a 0.18 /spl mu/m CMOS process.
Last updated on 05/04/2022