Evaluation of voltage interpolation to address process variations


Kevin Brownell, Gu Wei, and David Brooks. 3/2008. “Evaluation of voltage interpolation to address process variations.” In Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, Pp. 529–536. IEEE Press.


Abstract — Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks and shows that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. The analysis shows that the scheme can match the nominal delay target with a 10 % power cost, or for the same power budget, incur only a 9 % delay overhead after variations. I.

Last updated on 04/29/2022