We consider processor core complexity and its impli-cations for the power-performance efficiency of SMT and CMP architectures, exploring fundamental trade-offs be-tween the efficiency of multi-core architectures and the com-plexity of their cores from a power-performance perspec-tive. Taking pipeline depth and width as proxies for core complexity, we conduct power-performance simulations of several SMT and CMP architectures employing cores of varying complexity. Our analyses identify efficient pipeline dimensions and outline the implications of using a power-performance efficiency metric for core complexity. Collectively, our results suggest SMT architectures en-able efficient increases in pipeline dimensions and core complexity. Furthermore, reducing pipeline di-mensions in CMP cores is inefficient, assuming ideal power-performance scaling from voltage/frequency scal-ing and circuit re-tuning. Given these conclusions, we formulate guidelines for complexity effective design.