Digitally-enhanced phase-locking circuits


Hanumolu Kumar, Gu Wei, Moon Ku, and Kartikeya Mayaram. 9/16/2007. “Digitally-enhanced phase-locking circuits.” In 2007 IEEE Custom Integrated Circuits Conference, Pp. 361–368. IEEE. Publisher's Version


In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) implemented in deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed in detail. The implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs in digital systems requiring high-performance PLLs.
Last updated on 05/02/2022