A comprehensive phase-transfer model for delay-locked loops


Burnham R, Gu Wei, Yang Ken, and Hindi Haitham. 9/16/2007. “A comprehensive phase-transfer model for delay-locked loops.” In 2007 IEEE Custom Integrated Circuits Conference, Pp. 627–630. IEEE. Publisher's Version


This paper presents a comprehensive model for analyzing the behavior of an analog delay-locked loop (DLL). Unlike previous models, the proposed version includes both constant and variable phase-offset terms, making it possible to calculate jitter transfer characteristics, stability, and static phase errors from a single unified model. The topology more closely approximates the underlying architecture of the DLL, resulting in improved accuracy and enabling better tradeoffs between bandwidth, stability, and power.
Last updated on 05/02/2022