#  ESP Systolic Array Accelerator 

 



ESP Systolic Array Accelerator is an 8-bit integer, weight-stationary systolic array accelerator designed with the Catapult HLS flow in SystemC, with a reconfigurable array size (8, 16, or 32) and an AXI configuration interface.

GitHub: [github.com/harvard-acc/ESP\_Systolic\_Array\_Accelerator](https://github.com/harvard-acc/ESP_Systolic_Array_Accelerator)