Publications by Type: Conference Paper

2008
Chung Hayun, Liu Andrew, and Gu Wei. 9/21/2008. “A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13 $μ$m CMOS.” In 2008 IEEE Custom Integrated Circuits Conference, Pp. 563–566. IEEE. Publisher's VersionAbstract
This paper presents a 12.5-Gbps transmitter that uses a lookup table (LUT)-based equalizer to compensate for within-die imperfections. An equalization technique with 2x sampling is proposed to accommodate timing offsets in the multiphase clocks used for 8:1 serialization. LUT code remapping is also demonstrated to compensate for mismatch effects that introduce nonlinearity in the transmit DAC. Experimental results of a 7-bit resolution transmitter with 4-tap equalization, implemented in 0.13 mum CMOS, show the LUT-based equalizer can significantly improve the signal integrity of an otherwise closed eye for data transmitted at 12.5-Gbps.
A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13 $μ$m CMOS
Ankur Agrawal, Pavan Kumar Hanumolu, and Gu-Yeon Wei. 9/21/2008. “A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction.” In 2008 IEEE Custom Integrated Circuits Conference, Pp. 459–462. IEEE. Publisher's VersionAbstract
This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.
A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction
Xuning Chen, Gu Wei, and Peh Shiuan. 8/11/2008. “Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies.” In Proceedings of the 2008 international symposium on Low Power Electronics & Design, Pp. 277–282. Publisher's VersionAbstract
The need for low-power I/Os is widely recognized, as I/Os take up a significant portion of total chip power. In recent years, researchers have pointed to the potential system-level power savings that can be realized if dynamic voltage scalable I/Os are available. However, substantial challenges remain in building such links. This paper presents the design and implementation details of opto-electronic transceiver front-end blocks where supply voltage can scale from 1.2V to 0.6V with almost linearly scalable bandwidth from 8Gb/s to 4Gb/s, and power consumption from 36mW to 5mW in a 130nm CMOS process. To the best of our knowledge, this is the first circuit demonstration of voltage-scalable optical links. It demonstrates the feasibility of dynamic voltage scalable optical I/Os.
Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies
Gu Wei, David Brooks, Ali Khan, and Xiaoyao Liang. 8/11/2008. “Instruction-driven clock scheduling with glitch mitigation.” In Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), Pp. 357–362. ACM. Publisher's VersionAbstract
Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallower pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic power. Experimentally measured results from a 130 nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic power for shallower pipelines. While higher glitch power can severely diminish the power savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover power savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net power savings of 15% compared to an aggressively clock-gated design.
Instruction-driven clock scheduling with glitch mitigation
Xiaoyao Liang, Gu Wei, and David Brooks. 6/21/2008. “Revival: A variation-tolerant architecture using voltage interpolation and variable latency.” In Computer Architecture, 6/21/2008. ISCA'08. 35th International Symposium on, Pp. 191–202. IEEE. Publisher's VersionAbstract
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip, and among microarchitectural blocks within one core. Hence, it will be difficult to only rely on traditional frequency binning to efficiently cover the large variations that are expected. Furthermore, multiple voltage/frequency domains introduce significant hardware overhead and alone cannot address the full extent of delay variations expected in future multi-core systems. In this paper, we present ReVIVaL, which combines two fine-grained post-fabrication tuning techniques---voltage interpolation(VI) and variable latency(VL). We show that the frequency variation between chips, between cores on one chip, and between functional units within cores can be reduced to a very small range. The effectiveness of these techniques are further verified through experiments on test chips fabricated in a 130 nm CMOS process. Detailed architectural simulations of multi-core processors demonstrate significant performance and power advantages are possible by combining variable latency with voltage interpolation.
Revival: A variation-tolerant architecture using voltage interpolation and variable latency
Michael Karpelson, Gu Wei, and Wood J. 5/19/2008. “A review of actuation and power electronics options for flapping-wing robotic insects.” In 2008 IEEE international conference on robotics and automation, Pp. 779–786. IEEE. Publisher's VersionAbstract
Flapping-wing robotic insects require actuators with high power densities at centimeter to micrometer scales. Due to the low weight budget, the selection and design of the actuation mechanism needs to be considered in parallel with the design of the power electronics required to drive it. This paper explores the design space of flapping-wing microrobots weighing 1g and under by determining mechanical requirements for the actuation mechanism, analyzing potential actuation technologies, and discussing the design and realization of the required power electronics. Promising combinations of actuators and power circuits are identified and used to estimate microrobot performance.
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A review of actuation and power electronics options for flapping-wing robotic insects
Mark Hempstead, Gu Wei, and David Brooks. 5/18/2008. “System design considerations for sensor network applications.” In 2008 IEEE International Symposium on Circuits and Systems (ISCAS), Pp. 2566–2569. Seattle, WA: IEEE. Publisher's VersionAbstract
Systems research in the emerging space of wireless sensor networks has exploded. Researchers have deployed nodes composed of a wireless radio, MEMS sensors and low power computation for applications from medical sensing to volcanic monitoring. We must consider several requirements - including the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements - when designing devices for wireless sensor networks. An untethered, fully-integrated node that operates off of energy scavenged from the ambient environment is the ultimate goal. We take an application-driven approach to the design of a wireless sensor network node. Our approach addresses the event-driven nature that is characteristic of many sensor network workloads. We have completed a detailed architectural analysis of this space using a full-system simulator and RTL model. From this analysis, we chose to implement a design that best achieves the power goals and performance requirements of wireless sensor network applications.
System design considerations for sensor network applications
Simone Campanoni, Giovanni Agosta, and Stefano Reghizzi. 4/2008. “A parallel dynamic compiler for CIL bytecode.” In ACM Sigplan Notices, 4th ed., 43: Pp. 11-20. ACM. Publisher's VersionAbstract

Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the potentialities of their hardware parallelism.

At the same time, object code virtualization technologies are achieving a growing popularity, as they allow higher levels of software portability and reuse.

Thus, a virtual execution environment running on a multi-core processor has to run complex, high-level applications and to exploit as much as possible the underlying parallel hardware. We propose an approach that leverages on CMP features to expose a novel pipeline synchronization model for the internal threads of the dynamic compiler.

Thanks to compilation latency masking effect of the pipeline organization, our dynamic compiler, ILDJIT, is able to achieve significant speedups (26% on average) with respect to the baseline, when the underlying hardware exposes at least two cores.

A parallel dynamic compiler for CIL bytecode
Benjamin Lee and David Brooks. 3/2008. “Efficiency trends and limits from comprehensive microarchitectural adaptivity.” In ACM SIGARCH Computer Architecture News, 3rd ed., 43: Pp. 36–47. ACM. Publisher's VersionAbstract

ncreasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B point.

With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips3/w efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements.

Efficiency trends and limits from comprehensive microarchitectural adaptivity
Kevin Brownell, Gu Wei, and David Brooks. 3/2008. “Evaluation of voltage interpolation to address process variations.” In Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, Pp. 529–536. IEEE Press.Abstract

Abstract — Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks and shows that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. The analysis shows that the scheme can match the nominal delay target with a 10 % power cost, or for the same power budget, incur only a 9 % delay overhead after variations. I.

Evaluation of voltage interpolation to address process variations
Meeta Gupta, Krishna Rangan, Michael Smith, Gu Wei, and David Brooks. 2/16/2008. “DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors.” In 2008 IEEE 14th International Symposium on High Performance Computer Architecture, Pp. 381–392. IEEE. Publisher's VersionAbstract
Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to undesired effects, like timing violations, which may result in incorrect execution of applications. Several recent architectural solutions for inductive noise have been proposed that, unfortunately, have a strong correlation to the underlying power-delivery package model and require a feedback loop that is largely constrained by the voltage/current sensor characteristics. The resulting solutions are not robust across a wide range of microprocessor designs and packaging technologies. This paper proposes a Delayed-commit and rollback scheme (DeCoR) that guarantees correctness, insensitive to the package model or the responsiveness of the voltage sensors. In particular, our approach recovers from, rather than attempting to avoid, voltage emergencies. This approach incurs a small performance penalty when compared to an ideal machine that does not have voltage emergencies. We show that explicit checkpoint-recovery schemes, intended to handle infrequent events, e.g., radiation-induced soft errors, suffer from large performance overheads for frequently-occurring voltage emergencies. DeCoR requires very few modifications to modern processor designs, as it leverages the existing store queue and reorder buffers. Unlike conventional designs that conservatively protect all components of the processor from inductive noise with overly-large timing margins, our approach only requires conservative protection of the architected register state and cache write paths.
DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors
Wonyoung Kim, Meeta Gupta, Gu Wei, and David Brooks. 2/16/2008. “System level analysis of fast, per-core DVFS using on-chip switching regulators.” In 2008 IEEE 14th International Symposium on High Performance Computer Architecture, Pp. 123–134. Salt Lake City, UT, USA: Ieee. Publisher's VersionAbstract
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.
System level analysis of fast, per-core DVFS using on-chip switching regulators
Xiaoyao Liang, David Brooks, and Gu Wei. 2/3/2008. “A process-variation-tolerant floating-point unit with voltage interpolation and variable latency.” In 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, Pp. 404–623. San Francisco, CA, USA: IEEE. Publisher's VersionAbstract
This paper explores two fine-grained, post-fabrication circuit-tuning techniques to combat process variation for pipelined logic componentsrdquo voltage interpolation and variable latency. These techniques are applied to a single-precision floating-point unit (FPU) designed using a standard CAD synthesis flow in a 0.13 mum CMOS logic process with 8 metal layers. Measured results from fabricated chips show that both techniques provide wide frequency tuning range to deal with frequency fluctuations arising from process variations with minimal power overhead, and in some configurations, power savings.
A process-variation-tolerant floating-point unit with voltage interpolation and variable latency
2007
Ratnayake NS, Haratsch F, and Gu Wei. 12/2007. “A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders.” In IEEE GLOBECOM 2007-IEEE Global Telecommunications Conference, Pp. 265–270. IEEE. Publisher's VersionAbstract
A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Xiaoyao Liang, Ramon Canal, Gu Wei, and David Brooks. 12/2007. “Process variation tolerant 3T1D-based cache architectures.” In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Pp. 15–26. Chicago, IL, USA: IEEE Computer Society. Publisher's VersionAbstract
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continued technology scaling. In this paper, we propose new on-chip memory architectures based on novel 3T1D DRAM (3-transistor, 1-diode dynamic memory) cells. We provide a detailed comparison between 6T and 3T1D designs in the context of a L1 data cache. The effects of physical device variation on a 3T1D cache can be lumped into variation of data retention times. This paper proposes a range of cache refresh and placement schemes that are sensitive to retention time, and we show that most of the retention time variations can be masked by the microarchitecture when using these schemes. We have performed detailed circuit and architectural simulations assuming different degrees of variability in advanced technology nodes, and we show that the resulting memory architecture can tolerate large process variations with little or even no impact on performance when compared to ideal 6T SRAM designs. Furthermore, these designs are robust to memory cell stability issues and can achieve large power savings. These advantages make the new memory architectures a promising choice for on-chip variation-tolerant cache structures required for next generation microprocessors.
Process variation tolerant 3T1D-based cache architectures
Xiaoyao Liang, Ramon Canal, Gu Wei, and David Brooks. 12/2007. “Process variation tolerant register files based on dynamic memories.” In Workshop on Architectural Support for Gigascale Integration (ASGI-07) in conjunction with ISCA.Abstract
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continued technology scaling. In this paper, we propose new on-chip memory architectures based on novel 3T1D DRAM (3-transistor, 1-diode dynamic memory) cells. We provide a detailed comparison between 6T and 3T1D designs in the context of a L1 data cache. The effects of physical device variation on a 3T1D cache can be lumped into variation of data retention times. This paper proposes a range of cache refresh and placement schemes that are sensitive to retention time, and we show that most of the retention time variations can be masked by the microarchitecture when using these schemes.Ω
Process variation tolerant register files based on dynamic memories
Xiaoyao Liang, Kerem Turgay, and David Brooks. 11/4/2007. “Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques.” In Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, Pp. 824–830. IEEE Press. Publisher's VersionAbstract
The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and high-performance microprocessors incorporate large on-chip cache and similar SRAM-based or CAM-based structures, and these components can consume a significant fraction of the total chip power. Thus an accurate power modeling method for such structures is important in early architecture design studies. We present a unified architecture-level power modeling methodology for array structures which is highly-accurate, parameterizable, and technology scalable. We demonstrate the applicability of the model to different memory structures (SRAMs and CAMs) and include leakage-variability in advanced technologies. The power modeling approach is validated against HSPICE power simulation results, and we show power estimation accuracy within 5% of detailed circuit simulations.
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
Burnham R, Gu Wei, Yang Ken, and Hindi Haitham. 9/16/2007. “A comprehensive phase-transfer model for delay-locked loops.” In 2007 IEEE Custom Integrated Circuits Conference, Pp. 627–630. IEEE. Publisher's VersionAbstract
This paper presents a comprehensive model for analyzing the behavior of an analog delay-locked loop (DLL). Unlike previous models, the proposed version includes both constant and variable phase-offset terms, making it possible to calculate jitter transfer characteristics, stability, and static phase errors from a single unified model. The topology more closely approximates the underlying architecture of the DLL, resulting in improved accuracy and enabling better tradeoffs between bandwidth, stability, and power.
A comprehensive phase-transfer model for delay-locked loops
Hanumolu Kumar, Gu Wei, Moon Ku, and Kartikeya Mayaram. 9/16/2007. “Digitally-enhanced phase-locking circuits.” In 2007 IEEE Custom Integrated Circuits Conference, Pp. 361–368. IEEE. Publisher's VersionAbstract
In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) implemented in deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed in detail. The implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs in digital systems requiring high-performance PLLs.
Digitally-enhanced phase-locking circuits
Ratnayake NS, F Haratsch, and Gu Wei. 9/2007. “Serial Sum-Product Architecture for Low-Density Parity-Check Codes.” In 2007 16th International Conference on Computer Communications and Networks, Pp. 154–158. IEEE. Publisher's VersionAbstract
A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to check node messages sequentially, while the check node computations are broken up into several steps and computed on the fly. This bit node centric architecture requires considerably less memory compared to other serial architectures, including the check node centric architecture.
Serial Sum-Product Architecture for Low-Density Parity-Check Codes

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