Publications by Type: Book Chapter

Gu Wei, Horowitz Mark, and Jaeka Kim. 2002. “Energy-efficient design of high-speed links.” In Power Aware Design Methodologies, 8: Pp. 201–239. Springer, Boston, MA. Publisher's VersionAbstract

Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and describes some of the power vs. performance trade-offs associated with various design choices. The chapter then investigates various techniques that a designer may employ to reduce power consumption. Three examples of link designs and link building blocks found in the literature present energy-efficient implementations of these techniques.

Energy-efficient design of high-speed links
David Brooks and Margaret Martonosi. 1/1999. “Implementing application-specific cache-coherence protocols in configurable hardware.” In Network-Based Parallel Computing. Communication, Architecture, and Applications, Pp. 181–195. Springer. Publisher's VersionAbstract

Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best performance, not all parallel machines provide it. Instead, software layers using Shared Virtual Memory (SVM) can be built to enforce coherence at a higher level. In prior work, researchers have studied application-specific cache coherence protocols implemented either in SVM systems or as handlers run by programmable protocol processors. Since the protocols are specialized to the needs of a single application, they can be particularly helpful in reducing the long latencies and processing overhead that sometimes degrade performance in SVM systems. This paper studies implementing application-specific protocols in hardware, but not via an instruction-based protocol processor as is typical. Instead, we consider configurable implementations based on Field-Programmable Gate Arrays (FPGAs). This approach can be faster than software-based techniques and less expensive than some hardware-based techniques. We study one application, appbt, in detail, including a VHDL-level design of the configurable protocol design. We sketch out approaches for other applications as well. Implementing protocol operations in configurable hardware improves communication performance by roughly 11X for a 32-node system. While overall speedups are a more modest 12% our method is promising because of its flexibility and because it offers a new way of harnessing configurable hardware at the network interface, where it already exists or could be easily added to current systems.

Implementing application-specific cache-coherence protocols in configurable hardware