Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware


Brandon Reagen, Yakun Shao, Gu Wei, and David Brooks. 9/4/2013. “Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware.” In International Symposium on Low Power Electronics and Design (ISLPED). Publisher's Version


As the traditional performance gains of technology scaling diminish, one of the most promising directions is building special purpose fixed function hardware blocks, commonly referred to as accelerators. Accelerators have become prevalent in industrial SoC designs for their low power, high performance potential. In this work we explore thousands of implementations of classical software workloads in hardware. This thorough, detailed design space search of hardware accelerators gives architects a quantita- tive way to reason about the differences in implementations. The exploration presented in this work shows that the space is full of poor design choices. By thoroughly analyzing each benchmark, we show which provide the most performance when implemented in hardware given a fixed power budget and explain which design techniques work best for each workload.
Last updated on 04/26/2022