Multi-accelerator system development with the shrinkfit acceleration framework

Citation:

Michael Lyons, Gu Wei, and David Brooks. 10/19/2014. “Multi-accelerator system development with the shrinkfit acceleration framework.” In 2014 IEEE 32nd International Conference on Computer Design (ICCD), Pp. 75–82. IEEE. Publisher's Version

Abstract:

This paper introduces the ShrinkFit accelerator framework, which simplifies the design of systems combining multiple accelerators. A single ShrinkFit system design can be deployed to FPGAs large and small, without time-consuming architectural parameter surveys. We describe four ShrinkFit accelerators implemented for an FPGA-based robotic bee brain prototype and demonstrate the flexibility of ShrinkFit with low performance overheads (under 10% on average) and low resource overheads (0-8% for accelerators and under 2% for hard logic blocks).
Last updated on 04/25/2022