Measuring code optimization impact on voltage noise


Svilen Kanev, Timothy Jones, Gu Wei, David Brooks, and Vijay Reddi. 2013. “Measuring code optimization impact on voltage noise.” Workshop in Silicon Errors – System Effects (SELSE). Publisher's Version


In this paper, we characterize the impact of compiler optimizations on voltage noise. While intuition may suggest that the better processor utilization ensured by optimizing compilers results in a small amount of voltage variation, our measurements on a Intel Core2 Duo processor show the opposite – the majority of SPEC 2006 benchmarks exhibit more voltage droops when aggressively optimized. We show that this increase in noise could be sufficient for a net performance decrease in a typical-case, resilient design.
Last updated on 04/26/2022