A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation

Citation:

Helal M, Straayer Z, Gu Wei, and Perrott H. 6/14/2007. “A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation.” In 2007 IEEE Symposium on VLSI Circuits, Pp. 166–167. IEEE. Publisher's Version

Abstract:

This paper presents a 1.6 GHz multiplying delay-locked loop (MDLL) that leverages time-to-digital conversion and a digital correlation technique to achieve low deterministic jitter while still maintaining low random jitter. A proposed time-to-digital converter consists of a ring oscillator that is gated on and off to accurately measure time and scramble the measurement's residual error. Using a 50 MHz reference, the prototype system has measured reference spurs less than -59 dBc and an overall measured jitter of 1.41 ps.
Last updated on 05/02/2022