%0 Conference Paper %B 2007 IEEE Custom Integrated Circuits Conference %D 2007 %T A comprehensive phase-transfer model for delay-locked loops %A Burnham R %A Gu Wei %A Yang Ken %A Hindi Haitham %X This paper presents a comprehensive model for analyzing the behavior of an analog delay-locked loop (DLL). Unlike previous models, the proposed version includes both constant and variable phase-offset terms, making it possible to calculate jitter transfer characteristics, stability, and static phase errors from a single unified model. The topology more closely approximates the underlying architecture of the DLL, resulting in improved accuracy and enabling better tradeoffs between bandwidth, stability, and power. %B 2007 IEEE Custom Integrated Circuits Conference %I IEEE %P 627–630 %G eng %U https://doi.org/10.1109/CICC.2007.4405810