%0 Conference Paper %B 2008 IEEE Custom Integrated Circuits Conference %D 2008 %T A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction %A Agrawal, Ankur %A Hanumolu, Pavan Kumar %A Gu-Yeon Wei %X This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins. %B 2008 IEEE Custom Integrated Circuits Conference %I IEEE %P 459–462 %G eng %U https://doi.org/10.1109/CICC.2008.4672120