TY - CONF T1 - Multi-accelerator system development with the shrinkfit acceleration framework T2 - 2014 IEEE 32nd International Conference on Computer Design (ICCD) Y1 - 2014 A1 - Michael Lyons A1 - Gu Wei A1 - David Brooks AB - This paper introduces the ShrinkFit accelerator framework, which simplifies the design of systems combining multiple accelerators. A single ShrinkFit system design can be deployed to FPGAs large and small, without time-consuming architectural parameter surveys. We describe four ShrinkFit accelerators implemented for an FPGA-based robotic bee brain prototype and demonstrate the flexibility of ShrinkFit with low performance overheads (under 10% on average) and low resource overheads (0-8% for accelerators and under 2% for hard logic blocks). JF - 2014 IEEE 32nd International Conference on Computer Design (ICCD) PB - IEEE UR - https://doi.org/10.1109/ICCD.2014.6974665 ER -