TY - CONF T1 - Digitally-enhanced phase-locking circuits T2 - 2007 IEEE Custom Integrated Circuits Conference Y1 - 2007 A1 - Hanumolu Kumar A1 - Gu Wei A1 - Moon Ku A1 - Mayaram, Kartikeya AB - In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) implemented in deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed in detail. The implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs in digital systems requiring high-performance PLLs. JF - 2007 IEEE Custom Integrated Circuits Conference PB - IEEE UR - https://doi.org/10.1109/CICC.2007.4405753 ER -