TY - JOUR T1 - A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC–DC Converter JF - IEEE Transactions on VLSI Y1 - 2017 A1 - Sae Kyu Lee A1 - Tao Tong A1 - Xuan Zhang A1 - David Brooks A1 - Gu Wei KW - voltage-regulator KW - voltage-stacking AB - This paper presents a 16-core voltage-stacked system with adaptive frequency clocking (AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power delivery for multicore systems. Voltage stacking alleviates power delivery inefficiencies due to off-chip parasitics but adds complexity to combat internal voltage noise. To address the corresponding issue of internal voltage noise, the system utilizes an AFClk scheme with an efficient switched-capacitor dc-dc converter to mitigate noise on the stack layers and to improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation as well as the potential of voltage stacking as a highly efficient power delivery scheme. This paper also illustrates that augmenting the hardware techniques with intelligent workload allocation that exploits the inherent properties of voltage stacking can preemptively reduce the interlayer activity mismatch and improve system efficiency. VL - 25 UR - https://www.academia.edu/75987623/A_16_Core_Voltage_Stacked_System_With_Adaptive_Clocking_and_an_Integrated_Switched_Capacitor_DC_DC_Converter IS - 4 ER -