@conference {srinivasan2002optimizing,
	title = {Optimizing pipelines for power and performance},
	booktitle = {Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on},
	year = {2002},
	pages = {333{\textendash}344},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical power-performance model to derive optimal pipeline depth for a superscalar processor. The results are validated and further refined using detailed simulation based analysis. As part of the power-modeling methodology, we have developed equations that model the variation of energy as a function of pipeline depth. Our results using a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models.},
	url = {https://doi.org/10.1109/MICRO.2002.1176261},
	author = {Viji Srinivasan and David Brooks and Michael Gschwind and Pradip Bose and Victor Zyuban and Philip Strenski and Philip Emma}
}
@article {martonosi2002architecture,
	title = {Architecture-level power modeling with Wattch},
	journal = {Computer},
	volume = {35},
	year = {2002},
	pages = {64{\textendash}64},
	publisher = {IEEE Computer},
	author = {M Martonosi and David Brooks and V Tiwari}
}
@conference {buyuktosunoglu2002power,
	title = {Power-efficient issue queue design},
	booktitle = {Power aware computing},
	year = {2002},
	pages = {35{\textendash}58},
	publisher = {Kluwer Academic Publishers},
	organization = {Kluwer Academic Publishers},
	abstract = {<p>
	Increasing levels of power dissipation threaten to limit the performance gains of future high-end, out-of-order issue microprocessors. Therefore, it is imperative that designers devise techniques that significantly reduce the power dissipation of the key hardware structures on the chip without unduly compromising performance. Such a key structure in out-of-order designs is the issue queue. Although crucial in achieving high performance, the issue queues are often a major contributor to the overall power consumption of the chip, potentially affecting both thermal issues related to hot spots and energy issues related to battery life. In this chapter, we present two techniques that significantly reduce issue queue power while maintaining high performance operation. First, we evaluate the power savings achieved by implementing a CAM/RAM structure for the issue queue as an alternative to the more power-hungry latch-based issue queue used in many designs. We then present the microarchitecture and circuit design of an adaptive issue queue that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. We compare two different dynamic adaptation algorithms that use issue queue utilization and parallelism metrics in order to size the issue queue on-the-fly during execution. Together, these two techniques provide over a 70\% average reduction in issue queue power dissipation for a collection of the SPEC CPU2000 integer benchmarks, with only a 3\% overall performance degradation.
</p>
},
	url = {https://doi.org/10.1007/978-1-4757-6217-4_3},
	author = {Alper Buyuktosunoglu and David Albonesi and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook}
}
@inbook {wei2002energy,
	title = {Energy-efficient design of high-speed links},
	booktitle = {Power Aware Design Methodologies},
	volume = {8},
	year = {2002},
	pages = {201{\textendash}239},
	publisher = {Springer, Boston, MA},
	organization = {Springer, Boston, MA},
	abstract = {<p>
	Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and describes some of the power vs. performance trade-offs associated with various design choices. The chapter then investigates various techniques that a designer may employ to reduce power consumption. Three examples of link designs and link building blocks found in the literature present energy-efficient implementations of these techniques.
</p>
},
	url = {https://doi.org/10.1007/0-306-48139-1_8},
	author = {Gu  Wei and Horowitz Mark and Kim, Jaeka}
}
@report {bosepower,
	title = {Power-Performance and Power Swing Characterization in Adaptive Microarchitectures},
	year = {2002},
	institution = {IBM Research},
	abstract = {In this paper, we present an analysis of some of the fundamental power-performance tradeoffs in processors that employ adaptive techniques to vary sizes, bandwidths, clock-gating modes and clock frequencies. Initial expectations are set using simple analytical reasoning models. Later, simulation-based data is presented in the context of a simple, low-power super scalar processor prototype (called LPX) that is currently under development as a test vehicle. There are three fundamental issues that we attempt to address in this paper: (a) Does dynamic adaptation - in clocking or microarchitectural resources - help extend the power-performance efficiency range of wider-issue superscalars ? (b) What factors of power and power-density reductions are within practical reach in future adaptive processors ? (c) Does the presence of dynamic adaptation modes cause unacceptably large, worst-case power (or current) swings in affected sub-units ?},
	url = {https://dominoweb.draco.res.ibm.com/5762e1ce48772a0285256b800057b82d.html},
	author = {Pradip Bose and David Brooks and Viji Srinivasan and Philip Emma}
}
