@conference {helal2007low,
	title = {A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation},
	booktitle = {2007 IEEE Symposium on VLSI Circuits},
	year = {2007},
	pages = {166{\textendash}167},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper presents a 1.6 GHz multiplying delay-locked loop (MDLL) that leverages time-to-digital conversion and a digital correlation technique to achieve low deterministic jitter while still maintaining low random jitter. A proposed time-to-digital converter consists of a ring oscillator that is gated on and off to accurately measure time and scramble the measurement{\textquoteright}s residual error. Using a 50 MHz reference, the prototype system has measured reference spurs less than -59 dBc and an overall measured jitter of 1.41 ps.},
	url = {https://doi.org/10.1109/VLSIC.2007.4342700},
	author = {Helal M and Straayer Z and Gu  Wei and Perrott H}
}
