@conference {1490901, title = {Characterizing the Scalability of Graph Convolutional Networks on Intel{\textregistered} PIUMA}, booktitle = {IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}, year = {2023}, address = {Raleigh, North Carolina}, abstract = {

Large-scale Graph Convolutional Network (GCN) inference on traditional CPU/GPU systems is challenging due to a large memory footprint, sparse computational patterns, and irregular memory accesses with poor locality. Intel{\textquoteright}s Programmable Integrated Unified Memory Architecture (PIUMA) is designed to address these challenges for graph analytics. In this paper, a detailed characterization of GCNs is presented using the Open-Graph Benchmark (OGB) datasets to determine the viability of PIUMA as a potential solution to GCN scalability.

First, the extent of sparse matrix dense matrix multiplication~(SpMM) as a performance driver for GCN on CPU and GPU is explored, offering a methodology for predicting GCN behavior as a function of dataset characteristics. Second, an SpMM kernel optimized for PIUMA is described and investigated for sensitivity to system parameters including memory bandwidth, latency, and thread count. SpMM scalability on PIUMA is demonstrated, while the scalability limitations of a Xeon-optimized SpMM implementation are discussed. Finally, GCN performance is compared on PIUMA versus a Xeon CPU system and Ampere GPU system, showing impressive results on PIUMA for large-scale datasets.

}, author = {Matthew Adiletta and Jesmin Jahan Tithi and Emmanouil-Ioannis Farsarakis and Gerasimos Gerogiannis and Robert Adolf and Robert Benke and Sidharth Kashyap and Samuel Hsia and Kartik Lakhotia and Fabrizio Petrini and Gu-Yeon Wei and David Brooks} } @conference {1490906, title = {MP-Rec: Hardware-Software Co-Design to Enable Multi-Path Recommendation}, booktitle = {ASPLOS}, year = {2023}, address = {Vancouver, Canada}, abstract = {

Deep learning recommendation systems serve personalized content under diverse tail-latency targets and input-query loads. In order to do so, state-of-the-art recommendation models rely on terabyte-scale embedding tables to learn user preferences over large bodies of contents. The reliance on a fixed embedding representation of embedding tables not only imposes significant memory capacity and bandwidth requirements but also limits the scope of compatible system solutions. This paper challenges the assumption of fixed embedding representations by showing how synergies between embedding representations and hardware platforms can lead to improvements in both algorithmic- and system performance. Based on our characterization of various embedding representations, we propose a hybrid embedding representation that achieves higher quality embeddings at the cost of increased memory and compute requirements. To address the system performance challenges of the hybrid representation, we propose MP-Rec -- a co-design technique that exploits heterogeneity and dynamic selection of embedding representations and underlying hardware platforms.

On real system hardware, we demonstrate how matching custom accelerators, i.e., GPUs, TPUs, and IPUs, with compatible embedding representations can lead to 16.65x performance speedup. Additionally, in query-serving scenarios, MP-Rec achieves 2.49x and 3.76x higher correct prediction throughput and 0.19\% and 0.22\% better model quality on a CPU-GPU system for the Kaggle and Terabyte datasets, respectively.

}, url = {https://arxiv.org/abs/2302.10872}, author = {Samuel Hsia and Udit Gupta and Bilge Acun and Newsha Ardalani and Pan Zhong and Gu-Yeon Wei and David Brooks and Carole-Jean Wu} } @report {1456701, title = {Architectural Implications of Embedding Dimension During GCN on CPU and GPU}, year = {2022}, institution = {Harvard University}, address = {Cambridge}, abstract = {Graph Neural Networks (GNNs) are a class of neural networks designed to extract information from the graphical structure of data. Graph Convolutional Networks (GCNs) are a widely used type of GNN for \ transductive graph learning problems which apply convolution to learn information from graphs. GCN is a challenging algorithm from an architecture perspective due to inherent sparsity, low data reuse, and massive memory capacity requirements. Traditional neural algorithms exploit the high compute capacity of GPUs to achieve high performance for both inference and training. The architectural decision to use a GPU for GCN inference is a question explored in this work. GCN on both CPU and GPU was characterized in order to better understand the implications of graph size, embedding dimension, and sampling on performance.\ }, author = {Matthew Adiletta and David Brooks and Gu-Yeon Wei.} } @conference {1435478, title = {Zhuyi: Perception Processing Rate Estimation for Safety in Autonomous Vehicles}, booktitle = {ACM/IEEE Design Automation Conference (DAC)}, year = {2022}, address = {San Francisco, CA, USA}, author = {Yu-Shun Hsiao and Siva Kumar Sastry Hari and Micha{\l} Filipiuk and Timothy Tsai and Michael B. Sullivan and Vijay Janapa Reddi and Vasu Singh and Stephen W. Keckler} } @proceedings {1440953, title = {GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators}, year = {2022}, address = {Baltimore, Maryland, USA}, abstract = {This paper presents GoldenEye, a functional simulator with fault injection capabilities for common and emerging numerical formats, implemented for the PyTorch deep learning framework. Gold- enEye provides a unified framework for numerical format evaluation of DNNs, including traditional number systems such as fixed and floating point, as well as recent DNN-inspired formats such as block floating point and AdaptivFloat. Additionally, GoldenEye enables single- and multi- bit flips at various logical and functional points during a value{\textquoteright}s lifetime for resiliency analysis, including for the first time attention to numerical values{\textquoteright} hardware metadata. This paper describes Golden- Eye{\textquoteright}s technical design and implementation which make it an easy-to- use, extensible, versatile, and fast tool for dependability research and future DNN accelerator design. We showcase its utility with three case studies: a unifying platform for number system comparison and eval- uation, a design-space exploration heuristic for data type selection, and fast DNN reliability analysis for different error models. GoldenEye is open-sourced and available at: https://github.com/ma3mool/goldeneye.}, url = {https://doi.org/10.1109/DSN53405.2022.00031}, author = {Abdulrahman Mahmoud and Tambe, Thierry and Tarek Aloui and David Brooks and Gu-Yeon Wei} } @conference {1435471, title = {NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories}, booktitle = {2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)}, year = {2022}, address = {Seoul, South Korea}, abstract = {Repeated off-chip memory accesses to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy efficiency, and the actively expanding field of emerging, embeddable non-volatile memory (eNVM) technologies is providing many potential candidates to satisfy this need. Each technology proposal presents distinct trade-offs in terms of density, read, write, and reliability characteristics, and we present a comprehensive framework for navigating and quantifying these design trade-offs alongside realistic system constraints and application-level impacts. This work evaluates eNVM-based storage for a range of application and system contexts including machine learning on the edge, graph analytics, and general purpose cache hierarchy, in addition to describing a freely available (this http URL) set of tools for application experts, system designers, and device experts to better understand, compare, and quantify the next generation of embedded memory solutions.}, url = {https://doi.org/10.48550/arXiv.2109.01188}, author = {L. Pentecost and A. Hankin and M. Donato and M. Hempstead and G.-Y. Wei and D. Brooks} } @article {1435480, title = {Frl-fi: Transient fault analysis for federated reinforcement learning-based navigation systems}, journal = {2022 Design Automation and Test in Europe Conference (DATE)}, year = {2022}, abstract = {Swarm intelligence is being increasingly deployed in autonomous systems, such as drones and unmanned vehicles. Federated reinforcement learning (FRL), a key swarm intelligence paradigm where agents interact with their own environments and cooperatively learn a consensus policy while preserving privacy, has recently shown potential advantages and gained popularity. However, transient faults are increasing in the hardware system with continuous technology node scaling and can pose threats to FRL systems. Meanwhile, conventional redundancy-based protection methods are challenging to deploy on resource-constrained edge applications. In this paper, we experimentally evaluate the fault tolerance of FRL navigation systems at various scales with respect to fault models, fault locations, learning algorithms, layer types, communication intervals, and data types at both training and inference stages. We further propose two cost-effective fault detection and recovery techniques that can achieve up to 3.3x improvement in resilience with \<2.7\% overhead in FRL systems.}, url = {https://doi.org/10.48550/arXiv.2203.07276}, author = {Wan, Zishen and Aqeel Anwar and Abdulrahman Mahmoud and Tianyu Jia and Yu-Shun Hsiao and Vijay Janapa Reddi and Arijit Raychowdhury} } @conference {1435481, title = {OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge}, booktitle = {DATE: Design, Automation, and Test in Europe (DATE)}, year = {2022}, author = {Tianyu Jia and Yang, En-Yu and Yu-Shun Hsiao and Jonathan Cruz and David Brooks and Gu-Yeon Wei and Vijay Janapa Reddi} } @article {1435334, title = {Tabula: Efficiently Computing Nonlinear Activation Functions for Secure Neural Network Inference}, year = {2022}, abstract = {Multiparty computation approaches to private neural network inference require significant communication between server and client, incur tremendous runtime penalties, and cost massive storage overheads. The primary source of these expenses is garbled circuits operations for nonlinear activation functions (typically ReLU), which require on the order of kilobytes of data transfer for each individual operation and tens of kilobytes of preprocessing storage per operation per inference. We propose a replacement for garbled circuits: Tabula, an algorithm to securely and efficiently perform single operand nonlinear functions for private neural network inference. Tabula performs a one time client initialization procedure with the help of a trusted third party (or via using fully homomorphic encryption), operates over smaller finite fields whose elements are representable with less than 16 bits, and employs a lookup table which stores the encrypted results of nonlinear operations over secretly shared values. We show Tabula is secure under a semi-honest threat model, allowing it to be used as a replacement for garbled circuits operations. Our results show that for private neural network inference, Tabula eliminates communication by a factor of more than 50{\texttimes}, enables speedups over 10{\texttimes}, and reduces storage costs from O(n) to O(1).}, url = {https://doi.org/10.48550/arXiv.2203.02833}, author = {Maximilian Lam and Mitzenmacher, Michael and Vijay Janapa Reddi and Gu-Yeon Wei and David Brooks} } @article {1435523, title = {Learnings from a HLS-based High-Productivity Digital VLSI Flow}, journal = {In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE{\textquoteright}22)}, year = {2022}, abstract = {Thetwilight of Dennardscalinghasactivatedaglobaltrendtowards application-based hardware specialization. This trend is currently accelerating due to the surging democratization and deployment of machine learning on mobile and IoT compute platforms. At the same time, the growing complexity of specialized system-on-chips (SoCs) is levying a more laborious tax on ASIC companies{\textquoteright} design and verification efforts. High-level synthesis (HLS) is emerging as a foremost agile VLSI development methodology gaining increasing adoption in the hardware design community. However, concerns over Quality of Results (QoR) remain a key factor inhibiting more mainstream adoption of HLS. Obtaining optimal PPA outcomes can sometimes be an elusive or challenging task and strongly correlates with the syntactic approach of the high-level source code. In this paper, we aim to share the proven HLS practices we employed to raise the level of confidence in the post-silicon functional and performance expectations from our accelerator designs. In doing so, we recount some of the main challenges we encountered in our HLS-based hardware-software co-design journey and offer a few recommendations cultivated from our learnings. Finally, we posit on wheretheresearch opportunities to further improve design QoR and HLS user experience lie.}, url = {https://capra.cs.cornell.edu/latte22/paper/6.pdf}, author = {Tambe, Thierry and David Brooks and Gu-Yeon Wei} } @article {1435524, title = {Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface}, year = {2022}, abstract = {Specialized accelerators are increasingly used to meet the power-performance goals of emerging applications such as machine learning, image processing, and graph analysis. Existing accelerator programming methodologies using APIs have several limitations: (1) The application code lacks portability to other platforms and compiler frameworks; (2) the lack of integration of accelerator code in the compiler limits useful optimizations such as instruction selection and operator fusion; and (3) the opacity of the accelerator function semantics limits the ability to check the final code for correctness. The root of these limitations is the lack of a formal software/hardware interface specification for accelerators.
In this paper, we use the recently developed Instruction-Level Abstraction (ILA) for accelerators to serve this purpose, similar to how the Instruction Set Architecture (ISA) has been used as the software/hardware interface for processors. We propose a compiler flow termed D2A using the ILA and present a prototype that demonstrates this flow for deep learning (DL) applications. This prototype compiles programs from high-level domain-specific languages, e.g., PyTorch and MxNet, to multiple target accelerators with no target-specific extensions to the application or compiler - thus demonstrating application portability. It includes compiler optimizations through instruction selection using equality saturation-based flexible matching. Finally, we show checking the correctness of the resulting code through formal verification of individual matched operations and fully automated simulation-based validation of complete applications. The evaluation of the prototype compiler is based on six different DL applications and three different accelerators. Overall, this methodology lays the foundation for integrating accelerators in compiler flows using a formal software/hardware interface.}, url = {https://doi.org/10.48550/arXiv.2203.00218}, author = {Bo-Yuan Huang and Steven Lyubomirsky and Yi Li and Mike He and Tambe, Thierry and Gus Henry Smith and Akash Gaonkar and Vishal Canumalla and Gu-Yeon Wei and Aarti Gupta and Zachary Tatlock and Sharad Malik} } @conference {1435482, title = {Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems}, booktitle = {58th ACM/IEEE Design Automation Conference (DAC)}, year = {2021}, abstract = {Learning-based navigation systems are widely used in autonomous applications, such as robotics, unmanned vehicles and drones. Specialized hardware accelerators have been proposed for high-performance and energy-efficiency for such navigational tasks. However, transient and permanent faults are increasing in hardware systems and can catastrophically violate tasks safety. Meanwhile, traditional redundancy-based protection methods are challenging to deploy on resource-constrained edge applications. In this paper, we experimentally evaluate the resilience of navigation systems with respect to algorithms, fault models and data types from both RL training and inference. We further propose two efficient fault mitigation techniques that achieve 2x success rate and 39\% quality-of-flight improvement in learning-based navigation systems.}, url = {https://doi.org/10.48550/arXiv.2111.04957}, author = {Wan, Zishen and Aqeel Anwar and Yu-Shun Hsiao and Tianyu Jia and Vijay Janapa Reddi and Arijit Raychowdhury} } @article {1435526, title = {EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference}, journal = {IEEE/ACM International Symposium on Microarchitecture (MICRO 2021)}, year = {2021}, abstract = {Transformer-based language models such as BERT provide significant accuracy improvement for a multitude of natural language processing (NLP) tasks. However, their hefty computational and memory demands make them challenging to deploy to resource-constrained edge platforms with strict latency requirements. We present EdgeBERT, an in-depth algorithm-hardware co-design for latency-aware energy optimization for multi-task NLP. EdgeBERT employs entropy-based early exit predication in order to perform dynamic voltage-frequency scaling (DVFS), at a sentence granularity, for minimal energy consumption while adhering to a prescribed target latency. Computation and memory footprint overheads are further alleviated by employing a calibrated combination of adaptive attention span, selective network pruning, and floating-point quantization. Furthermore, in order to maximize the synergistic benefits of these algorithms in always-on and intermediate edge computing settings, we specialize a 12nm scalable hardware accelerator system, integrating a fast-switching low-dropout voltage regulator (LDO), an all-digital phase-locked loop (ADPLL), as well as, high-density embedded non-volatile memories (eNVMs) wherein the sparse floating-point bit encodings of the shared multi-task parameters are carefully stored. Altogether, latency-aware multi-task NLP inference acceleration on the EdgeBERT hardware system generates up to 7x, 2.5x, and 53x lower energy compared to the conventional inference without early stopping, the latency-unbounded early exit approach, and CUDA adaptations on an Nvidia Jetson Tegra X2 mobile GPU, respectively.}, url = {https://doi.org/10.48550/arXiv.2011.14203}, author = {Tambe, Thierry and Coleman Hooper and Lillian Pentecost and Tianyu Jia and Yang, En-Yu and Marco Donato and Victor Sanh and Paul Whatmough and Alexander M. Rush and David Brooks and Gu-Yeon Wei} } @proceedings {1435470, title = {Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories}, year = {2021}, address = {Boston, MA, USA}, abstract = {The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device characteristics, programming schemes, and memory array architecture, and explore different design choices to optimize performance, energy, area, and accuracy metrics for critical data-intensive workloads. From our cross-stack design exploration, we find that we can store DNN weights and social network graphs at a density of over 8MB/mm 2 and sub-2ns read access latency without loss in application accuracy.}, url = {https://doi.org/10.1109/ISLPED52811.2021.9502489}, author = {M. M. Sharifi and L. Pentecost and R. Rajaei and A. Kazemi and Q. Lou and G.-Y. Wei and D. Brooks and K. Ni and X. S. Hu and M. Niemier and M. Donato} } @article {1435335, title = {Gradient Disaggregation: Breaking Privacy in Federated Learning by Reconstructing the User Participant Matrix}, year = {2021}, abstract = {We show that aggregated model updates in federated learning may be insecure. An untrusted central server may disaggregate user updates from sums of updates across participants given repeated observations, enabling the server to recover privileged information about individual users{\textquoteright} private training data via traditional gradient inference attacks. Our method revolves around reconstructing participant information (e.g: which rounds of training users participated in) from aggregated model updates by leveraging summary information from device analytics commonly used to monitor, debug, and manage federated learning systems. Our attack is parallelizable and we successfully disaggregate user updates on settings with up to thousands of participants. We quantitatively and qualitatively demonstrate significant improvements in the capability of various inference attacks on the disaggregated updates. Our attack enables the attribution of learned properties to individual users, violating anonymity, and shows that a determined central server may undermine the secure aggregation protocol to break individual users{\textquoteright} data privacy in federated learning.
\ }, url = {https://doi.org/10.48550/arXiv.2106.06089}, author = {Maximilian Lam and Gu-Yeon Wei and David Brooks and Vijay Janapa Reddi and Mitzenmacher, Michael} } @article {1435484, title = {Mavfi: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles}, year = {2021}, abstract = {Reliability and safety are critical in autonomous machine services, such as autonomous vehicles and aerial drones. In this paper, we first present an open-source Micro Aerial Vehicles (MAVs) reliability analysis framework, MAVFI, to characterize transient fault{\textquoteright}s impacts on the end-to-end flight metrics, e.g., flight time, success rate. Based on our framework, it is observed that the end-to-end fault tolerance analysis is essential for characterizing system reliability. We demonstrate the planning and control stages are more vulnerable to transient faults than the visual perception stage in the common "Perception-Planning-Control (PPC)" compute pipeline. Furthermore, to improve the reliability of the MAV system, we propose two low overhead anomaly-based transient fault detection and recovery schemes based on Gaussian statistical models and autoencoder neural networks. We validate our anomaly fault protection schemes with a variety of simulated photo-realistic environments on both Intel i9 CPU and ARM Cortex-A57 on Nvidia TX2 platform. It is demonstrated that the autoencoder-based scheme can improve the system reliability by 100\% recovering failure cases with less than 0.0062\% computational overhead in best-case scenarios. In addition, MAVFI framework can be used for other ROS-based cyber-physical applications and is open-sourced at\ this https URL.}, url = {https://doi.org/10.48550/arXiv.2105.12882}, author = {Yu-Shun Hsiao and Wan, Zishen and Tianyu Jia and Radhika Ghosal and Arijit Raychowdhury and David Brooks and Gu-Yeon Wei and Vijay Janapa Reddi} } @article {1434918, title = {RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance}, journal = {MICRO {\textquoteright}21: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture}, year = {2021}, pages = {870{\textendash}884}, abstract = {Deep learning recommendation systems must provide high quality, personalized content under strict tail-latency targets and high system loads. This paper presents RecPipe, a system to jointly optimize recommendation quality and inference performance. Central to RecPipe is decomposing recommendation models into multi-stage pipelines to maintain quality while reducing compute complexity and exposing distinct parallelism opportunities. RecPipe implements an inference scheduler to map multi-stage recommendation engines onto commodity, heterogeneous platforms (e.g., CPUs, GPUs).While the hardware-aware scheduling improves ranking efficiency, the commodity platforms suffer from many limitations requiring specialized hardware. Thus, we design RecPipeAccel (RPAccel), a custom accelerator that jointly optimizes quality, tail-latency, and system throughput. RPAc-cel is designed specifically to exploit the distinct design space opened via RecPipe. In particular, RPAccel processes queries in sub-batches to pipeline recommendation stages, implements dual static and dynamic embedding caches, a set of top-k filtering units, and a reconfigurable systolic array. Com-pared to prior-art and at iso-quality, we demonstrate that RPAccel improves latency and throughput by 3x and 6x.}, url = {https://doi.org/10.48550/arXiv.2105.08820}, author = {Udit Gupta and Hsia, Samuel and Jeff Zhang and Wilkening, Mark and Javin Pombra and Hsien-Hsin S. Lee and Gu-Yeon Wei and Carole-Jean Wu and David Brooks} } @article {1435529, title = {Robomorphic Computing: A Design Methodology for Domain-Specific Accelerators Parameterized by Robot Morphology}, journal = {Architectural Support for Programming Languages and Operating Systems (ASPLOS{\textquoteright}21)}, year = {2021}, pages = {674{\textendash}686}, abstract = {

Robotics applications have hard time constraints and heavy computational burdens that can greatly benefit from domain-specific hardware accelerators. For the latency-critical problem of robot motion planning and control, there exists a performance gap of at least an order of magnitude between joint actuator response rates and state-of-the-art software solutions. Hardware acceleration can close this gap, but it is essential to define automated hardware design flows to keep the design process agile as applications and robot platforms evolve. To address this challenge, we introduce robomorphic computing: a methodology to transform robot morphology into a customized hardware accelerator morphology. We (i) present this design methodology, using robot topology and structure to exploit parallelism and matrix sparsity patterns in accelerator hardware; (ii) use the methodology to generate a parameterized accelerator design for the gradient of rigid body dynamics, a key kernel in motion planning; (iii) evaluate FPGA and synthesized ASIC implementations of this accelerator for an industrial manipulator robot; and (iv) describe how the design can be automatically customized for other robot models. Our FPGA accelerator achieves speedups of 8{\texttimes} and 86{\texttimes} over CPU and GPU when executing a single dynamics gradient computation. It maintains speedups of 1.9{\texttimes} to 2.9{\texttimes} over CPU and GPU, including computation and I/O round-trip latency, when deployed as a coprocessor to a host CPU for processing multiple dynamics gradient computations. ASIC synthesis indicates an additional 7.2{\texttimes} speedup for single computation latency. We describe how this principled approach generalizes to more complex robot platforms, such as quadrupeds and humanoids, as well as to other computational kernels in robotics, outlining a path forward for future robomorphic computing accelerators.

}, url = {https://doi.org/10.1145/3445814.3446746}, author = {Sabrina M. Neuman and Brian Plancher and Thomas Bourgeat and Tambe, Thierry and Srinivas Devadas and Vijay Janapa Reddi} } @article {1435528, title = {From DSLs to Accelerator-rich Platform Implementations: Addressing the Mapping Gap}, journal = {Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE{\textquoteright}21)}, year = {2021}, url = {https://capra.cs.cornell.edu/latte21/}, author = {Bo-Yuan Huang and Steven Lyubomirsky and Tambe, Thierry and Yi Li and Mike He and Gus Smith and Gu-Yeon Wei and Aarti Gupta and Sharad Malik and Zachary Tatlock} } @article {1435525, title = {A 25mm2 SoC for IoT Devices with 18ms Noise Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET}, journal = {International Solid-State Circuits Conference (ISSCC{\textquoteright}21)}, year = {2021}, abstract = {Automatic speech recognition (ASR) using deep learning is essential for user interfaces on IoT devices. However, previously published ASR chips [4-7] do not consider realistic operating conditions, which are typically noisy and may include more than one speaker. Furthermore, several of these works have implemented only small-vocabulary tasks, such as keyword-spotting (KWS), where context-blind deep neural network (DNN) algorithms are adequate. However, for large-vocabulary tasks (e.g., \>100k words), the more complex bidirectional RNNs with an attention mechanism [1] provide context learning in long sequences, which improve ASR accuracy by up to 62\% on the 200kwords LibriSpeech dataset, compared to a simpler unidirectional RNN (Fig. 9.8.1). Attention-based networks emphasize the most relevant parts of the source sequence during each decoding time step. In doing so, the encoder sequence is treated as a soft-addressable memory whose positions are weighted based on the state of the decoder RNN. Bidirectional RNNs learn past and future temporal information by concatenating forward and backward time steps.}, url = {https://doi.org/10.1109/ISSCC42613.2021.9366062}, author = {Tambe, Thierry and Yang, En-Yu and Glenn G. Ko and Chai, Yuji and Coleman Hooper and Marco Donato and Paul N. Whatmough and Alexander M. Rush and David Brooks and Gu-Yeon Wei} } @article {1434916, title = {RecSSD: Near Data Processing for Solid State Drive Based Recommendation Inference}, journal = {ASPLOS 2021: Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems}, year = {2021}, pages = {717{\textendash}729}, abstract = {Neural personalized recommendationmodelsareusedacrossawide Samuel Hsia Harvard University Cambridge, Massachusetts, USA shsia@g.harvard.edu David Brooks Harvard University Cambridge, Massachusetts, USA dbrooks@eecs.harvard.edu USA. ACM, New York, NY, USA, 13 pages. https://doi.org/10.1145/3445814. 3446763 variety of datacenter applications including search, social media, and entertainment. State-of-the-art models comprise large embedding tables that have billions of parameters requiring large memory capacities. Unfortunately, large and fast DRAM-based memories levy high infrastructure costs. Conventional SSD-based storage solutions offer an order of magnitude larger capacity, but have worse read latency and bandwidth, degrading inference performance. RecSSD is a near data processing based SSD memory system customized for neural recommendation inference that reduces end-to-end model inference latency by 2{\texttimes} compared to using COTS SSDs across eight industry-representative models.}, url = {https://doi.org/10.48550/arXiv.2102.00075}, author = {Wilkening, Mark and Udit Gupta and Hsia, Samuel and Caroline Trippel and Carole-Jean Wu and David Brooks and Gu-Yeon Wei} } @article {1435337, title = {QuaRL: Quantization for Sustainable Reinforcement Learning}, year = {2020}, abstract = {Deep reinforcement learning continues to show tremendous potential in achieving tasklevel autonomy, however, its computational and energy demands remain prohibitively high. In this paper, we tackle this problem by applying quantization to reinforcement learning. To that end, we introduce a novel Reinforcement Learning (RL) training paradigm, ActorQ, to speed up actor-learner distributed RL training. ActorQ leverages 8-bit quantized actors to speed up data collection without affecting learning convergence. Our quantized distributed RL training system, ActorQ, demonstrates end-to-end speedups of \> 1.5 {\texttimes}- 2.5 {\texttimes}, and faster convergence over full precision training on a range of tasks (Deepmind Control Suite) and different RL algorithms (D4PG, DQN). Furthermore, we compare the carbon emissions (Kgs of CO2) of ActorQ versus standard reinforcement learning on various tasks. Across various settings, we show that ActorQ enables more environmentally friendly reinforcement learning by achieving 2.8{\texttimes} less carbon emission and energy compared to training RLagents in full-precision. Finally, we demonstrate empirically that aggressively quantized RL-policies (up to 4/5 bits) enable significant speedups on quantization-friendly (supports native quantization) resource-constrained edge devices, without degrading accuracy. We believe that this is the first of many future works on enabling computationally /energy efficient and sustainable reinforcement learning. The source code for QuaRL is available here: https://github.com/harvard-edge/QuaRL.}, url = {https://doi.org/10.48550/arXiv.1910.01055}, author = {Krishnan, Srivatsan and Maximilian Lam and Sharad Chitlangia and Wan, Zishen and Gabriel Barth-Maron and Faust, Aleksandra and Vijay Janapa Reddi} } @conference {1379396, title = {Cross-Stack Workload Characterization of Deep Recommendation Systems}, booktitle = {2020 IEEE International Symposium on Workload Characterization (IISWC)}, year = {2020}, month = {27 Oct 2020}, abstract = {

Deep learning based recommendation systems form the backbone of most personalized cloud services. Though the computer architecture community has recently started to take notice of deep recommendation inference, the resulting solutions have taken wildly different approaches - ranging from near memory processing to at-scale optimizations. To better design future hardware systems for deep recommendation inference, we must first systematically examine and characterize the underlying systems-level impact of design decisions across the different levels of the execution stack. In this paper, we characterize eight industry-representative deep recommendation models at three different levels of the execution stack: algorithms and software, systems platforms, and hardware microarchitectures. Through this cross-stack characterization, we first show that system deployment choices (i.e., CPUs or GPUs, batch size granularity) can give us up to 15x speedup. To better understand the bottlenecks for further optimization, we look at both software operator usage breakdown and CPU frontend and backend microarchitectural inefficiencies. Finally, we model the correlation between key algorithmic model architecture features and hardware bottlenecks, revealing the absence of a single dominant algorithmic component behind each hardware bottleneck.

}, url = {https://arxiv.org/abs/2010.05037}, author = {Hsia, Samuel and Udit Gupta and Wilkening Mark and Carole Wu and Gu-Yeon Wei and David Brooks} } @article {reagen2020cheetah, title = {Cheetah: Optimizations and Methods for PrivacyPreserving Inference via Homomorphic Encryption}, year = {2020}, abstract = {As the application of deep learning continues to grow, so does the amount of data used to make predictions. While traditionally, big-data deep learning was constrained by computing performance and off-chip memory bandwidth, a new constraint has emerged: privacy. One solution is homomorphic encryption (HE). Applying HE to the client-cloud model allows cloud services to perform inference directly on the client{\textquoteright}s encrypted data. While HE can meet privacy constraints, it introduces enormous computational challenges and remains impractically slow in current systems.
This paper introduces Cheetah, a set of algorithmic and hardware optimizations for HE DNN inference to achieve plaintext DNN inference speeds. Cheetah proposes HE-parameter tuning optimization and operator scheduling optimizations, which together deliver 79x speedup over the state-of-the-art. However, this still falls short of plaintext inference speeds by almost four orders of magnitude. To bridge the remaining performance gap, Cheetah further proposes an accelerator architecture that, when combined with the algorithmic optimizations, approaches plaintext DNN inference speeds. We evaluate several common neural network models (e.g., ResNet50, VGG16, and AlexNet) and show that plaintext-level HE inference for each is feasible with a custom accelerator consuming 30W and 545mm^2.}, url = {https://doi.org/10.48550/arXiv.2006.00505}, author = {Brandon Reagen and Choi, Wooseok and Ko, Yeongil and Lee, Vincent and Gu Wei and Lee S and David Brooks} } @article {krishnan2020sky, title = {The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines}, journal = {IEEE Computer Architecture Letters}, volume = {19}, year = {2020}, pages = {38{\textendash}42}, publisher = {IEEE}, abstract = {We introduce the {\textquotedblleft}Formula-1{\textquotedblright} (F-1) roofline model to understand the role of computing in aerial autonomous machines. The model provides insights by exploiting the fundamental relationships between various components in an aerial robot, such as sensor framerate, compute performance, and body dynamics (physics). F-1 serves as a tool that can aid computer and cyber-physical system architects to understand the optimal design (or selection) of various components in the development of autonomous machines.}, url = {https://doi.org/10.1109/LCA.2020.2981022}, author = {Krishnan, Srivatsan and Wan, Zishen and Bhardwaj, Kshitij and Paul Whatmough and Faust, Aleksandra and Gu Wei and David Brooks and Vijay Reddi} } @conference {Ko2020b, title = {A Scalable Bayesian Inference Accelerator for Unsupervised Learning}, booktitle = {IEEE Hot Chips 31 Symposium}, year = {2020}, address = {Palo Alto, CA, USA}, abstract = {This article consists only of a collection of slides from the author{\textquoteright}s conference presentation.}, keywords = {accelerators, bayesian inference, deep learning}, url = {https://doi.org/10.1109/HCS49909.2020.9220686}, author = {Ko, Glenn and Chai, Yuji and Marco Donato and Paul Whatmough and Tambe Thierry and Rob Rutenbar and Gu Wei and Gu Wei} } @conference {bhardwaj2020comprehensive, title = {A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs}, booktitle = {Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design}, year = {2020}, pages = {145{\textendash}150}, abstract = {

Modern systems-on-chip (SoCs) include not only general-purpose CPUs but also specialized hardware accelerators. Typically, there are three coherence model choices to integrate an accelerator with the memory hierarchy:\ no coherence, coherent with the last-level cache (LLC), and\ private cache based full coherence.\ However, there has been very limited research on finding which coherence models are optimal for the accelerators of a complex many-accelerator SoC. This paper focuses on determining a\ cost-aware coherence interface\ for an SoC and its target application: find the best coherence models for the accelerators that optimize their power and performance, considering both workload characteristics and system-level contention. A novel comprehensive methodology is proposed that uses Bayesian optimization to efficiently find the cost-aware coherence interfaces for SoCs that are modeled using the gem5-Aladdin architectural simulator. For a complete analysis, gem5-Aladdin is extended to support LLC coherence in addition to already-supported no coherence and full coherence. For a heterogeneous SoC targeting applications with varying amount of accelerator-level parallelism, the proposed framework rapidly finds cost-aware coherence interfaces that show significant performance and power benefits over the other commonly-used coherence interfaces.

}, url = {https://doi.org/10.1145/3370748.3406564}, author = {Bhardwaj, Kshitij and Havasi, Marton and Yao, Yuan and David Brooks and Jos{\'e} Lobato and Gu Wei} } @article {Whatmough2020, title = {CHIPKIT: An agile, reusable open-source framework for rapid test chip development}, journal = {IEEE Micro}, volume = {40}, year = {2020}, pages = {32 - 40}, abstract = {The current trend for domain-specific architectures (DSAs) has led to renewed interest in research test chips to demonstrate new specialized hardware. Tape-outs also offer huge pedagogical value garnered from real hands-on exposure to the whole system stack. However, successful tape-outs demand hard-earned experience, and the design process is time consuming and fraught with challenges. Therefore, custom chips have remained the preserve of a small number of research groups, typically focused on circuit design research. This paper describes the CHIPKIT framework. We describe a reusable SoC subsystem which provides basic IO, an on-chip programmable host, memory and peripherals. This subsystem can be readily extended with new IP blocks to generate custom test chips. We also present an agile RTL development flow, including a code generation tool calledVGEN. Finally, we outline best practices for full-chip validation across the entire design cycle.}, keywords = {accelerators}, url = {https://arxiv.org/abs/2001.04504}, author = {Paul Whatmough and Marco Donato and Ko, Glenn and David Brooks and Gu-Wei} } @conference {Tambe2020, title = {Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference}, year = {2020}, note = {Best paper award}, publisher = {Design Automation Conference (DAC 2020)}, organization = {Design Automation Conference (DAC 2020)}, address = {San Francisco, CA, USA}, abstract = {Conventional hardware-friendly quantization methods, such asfixed-point or integer, tend to perform poorly at very low preci-sion as their shrunken dynamic ranges cannot adequately capturethe wide data distributions commonly seen in sequence transduc-tion models. We present an algorithm-hardware co-design centeredaround a novel floating-point inspired number format,AdaptivFloat,that dynamically maximizes and optimally clips its available dy-namic range, at a layer granularity, in order to create faithful encod-ings of neural network parameters. AdaptivFloat consistently pro-duces higher inference accuracies compared to block floating-point,uniform, IEEE-like float or posit encodings at low bit precision (<=8-bit) across a diverse set of state-of-the-art neural networks, ex-hibiting narrow to wide weight distribution. Notably, at 4-bit weightprecision, only a 2.1 degradation in BLEU score is observed on theAdaptivFloat-quantized Transformer network compared to totalaccuracy loss when encoded in the above-mentioned prominentdatatypes. Furthermore, experimental results on a deep neural net-work (DNN) processing element (PE), exploiting AdaptivFloat logicin its computational datapath, demonstrate per-operation energyand area that is 0.9{\texttimes}and 1.14{\texttimes}, respectively, that of an equivalentbit width NVDLA-like integer-based PE.}, keywords = {deep learning, dnn, hardware support for machine learning}, url = {https://doi.org/10.1109/DAC18072.2020.9218516}, author = {Tambe, Thierry and En-Yang and Wan, Zishen and Deng, Yuntian and Vijay Reddi and Rush, Alexander and David Brooks and Gu-Yeon Wei} } @conference {tumeo2020software, title = {Software Defined Accelerators From Learning Tools Environment}, booktitle = {2020 57th ACM/IEEE Design Automation Conference (DAC)}, year = {2020}, pages = {1{\textendash}6}, publisher = {IEEE}, organization = {IEEE}, abstract = {Next generation systems, such as edge devices, will need to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. In this paper we present the Software Defined Accelerators From Learning Tools Environment (SODALITE), an automated open source high-level ML framework-to-verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets. The SODALITE approach will implement optimal designs by seamlessly combining custom components generated through high-level synthesis (HLS) with templated and fully tunable Intellectual Properties (IPs) and macros, integrated in an extendable resource library. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimensions.}, url = {https://doi.org/10.1109/DAC18072.2020.9218489}, author = {Tumeo, Antonino and Minutoli, Marco and Castellana, Giovanni and Manzano, Joseph and Amatya, Vinay and David Brooks and Gu Wei} } @conference {Ko2020, title = {A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm}, booktitle = {IEEE Symposium on VLSI Circuits (VLSI)}, year = {2020}, abstract = {This paper describes a 16nm programmable accelerator for unsupervised probabilistic machine perception tasks that performs Bayesian inference on probabilistic models mapped onto a 2D Markov Random Field, using MCMC. Exploiting two degrees of parallelism, it performs Gibbs sampling inference at up to 1380{\texttimes} faster with 1965{\texttimes} less energy than an Arm Cortex-A53 on the same SoC, and 1.5{\texttimes} faster with 6.3{\texttimes} less energy than an embedded FPGA in the same technology. At 0.8V, it runs at 450MHz, producing 44.6 MSamples/s at 0.88 nJ/sample.}, keywords = {accelerators, bayesian inference, deep learning}, url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162784}, author = {Ko, Glenn and Chai, Yuji and Marco Donato and Paul Whatmough and Tambe, Thierry and Rob Rutenbar and David Brooks and Gu-Yeon Wei} } @conference {Ke2020, title = {RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing}, year = {2020}, publisher = {The 47th IEEE/ACM International Symposium on Computer Architecture (ISCA 2020)}, organization = {The 47th IEEE/ACM International Symposium on Computer Architecture (ISCA 2020)}, abstract = {Personalized recommendation systems leverage deep learning models and account for the majority of data center AI cycles. Their performance is dominated by memory-bound sparse embedding operations with unique irregular memory access patterns that pose a fundamental challenge to accelerate. This paper proposes a lightweight, commodity DRAM compliant, near-memory processing solution to accelerate personalized recommendation inference. The in-depth characterization of production-grade recommendation models shows that embedding operations with high model-, operator- and data-level parallelism lead to memory bandwidth saturation, limiting recommendation inference performance. We propose RecNMP which provides a scalable solution to improve system throughput, supporting a broad range of sparse embedding models. RecNMP is specifically tailored to production environments with heavy co-location of operators on a single server. Several hardware/software co-optimization techniques such as memory-side caching, table-aware packet scheduling, and hot entry profiling are studied, resulting in up to 9.8x memory latency speedup over a highly-optimized baseline. Overall, RecNMP offers 4.2x throughput improvement and 45.8\% memory energy savings.}, keywords = {accelerators, deep learning, neural network accelerators, Recommendation}, url = {https://doi.org/10.48550/arXiv.1912.12953 }, author = {Liu Ke and Udit Gupta and Carole-Jean Wu and Benjamin Cho and Mark Hempstead and Brandon Reagen and Xuan Zhang and David Brooks and Vikas Chandra and Utku Diril and Amin Firoozshahian and Kim Hazelwood and Bill Jia and Hsien-Hsin Lee and Meng Li and Bert Maher and Dheevatsa Mudigere and Maxim Naumov and Martin Schatz and Mikhail Smelyanskiy and Xiaodong Wang} } @article {mattson2020mlperf, title = {MLPerf: An industry standard benchmark suite for machine learning performance}, journal = {IEEE Micro}, volume = {40}, year = {2020}, pages = {8{\textendash}16}, publisher = {IEEE}, abstract = {In this article, we describe the design choices behind MLPerf, a machine learning performance benchmark that has become an industry standard. The first two rounds of the MLPerf Training benchmark helped drive improvements to software-stack performance and scalability, showing a 1.3{\texttimes} speedup in the top 16-chip results despite higher quality targets and a 5.5{\texttimes} increase in system scale. The first round of MLPerf Inference received over 500 benchmark results from 14 different organizations, showing growing adoption.}, url = {https://doi.org/10.1109/MM.2020.2974843}, author = {Mattson Peter and Vijay Reddi and Cheng, Christine and Coleman, Cody and Diamos, Greg and Kanter, David and Micikevicius, Paulius and Patterson, David and Schmuelling, Guenther and Tang, Hanlin and Gu-Yeon Wei and Carole-Jean Wu} } @article {1435336, title = {Precision Batching: Bitserial Decomposition for Efficient Neural Network Inference on GPUs}, year = {2020}, abstract = {We present PrecisionBatching, a quantized inference algorithm for speeding up neural network execution on traditional hardware platforms at low bitwidths without the need for retraining or recalibration. PrecisionBatching decomposes a neural network into individual bitlayers and accumulates them using fast 1-bit operations while maintaining activations in full precision. PrecisionBatching not only facilitates quantized inference at low bitwidths (\< 8 bits) without the need for retraining/recalibration, but also 1) enables traditional hardware platforms the ability to realize inference speedups at a finer granularity of quantization (e.g: 1-16 bit execution) and 2) allows accuracy and speedup tradeoffs at runtime by exposing the number of bitlayers to accumulate as a tunable parameter. Across a variety of applications (MNIST, language modeling, natural language inference) and neural network architectures (fully connected, RNN, LSTM), PrecisionBatching yields end-to-end speedups of over 8x on a GPU within a \< 1\% error margin of the full precision baseline, outperforming traditional 8-bit quantized inference by over 1.5x-2x at the same error tolerance.}, url = {https://doi.org/10.48550/arXiv.2003.00822}, author = {Maximilian Lam and Zachary Yedidia and Colby Banbury and Vijay Janapa Reddi} } @conference {Gupta2020, title = {The Architectural Implications of Facebook{\textquoteright}s DNN-based Personalized Recommendation}, year = {2020}, publisher = {The 26th IEEE International Symposium on High-Performance Computer Architecture}, organization = {The 26th IEEE International Symposium on High-Performance Computer Architecture}, abstract = {The widespread application of deep learning has changed the landscape of computation in the data center. In particular, personalized recommendation for content ranking is now largely accomplished leveraging deep neural networks. However, despite the importance of these models and the amount of compute cycles they consume, relatively little research attention has been devoted to systems for recommendation. To facilitate research and to advance the understanding of these workloads, this paper presents a set of real-world, production-scale DNNs for personalized recommendation coupled with relevant performance metrics for evaluation. In addition to releasing a set of open-source workloads, we conduct in-depth analysis that underpins future system design and optimization for at-scale recommendation: Inference latency varies by 60\% across three Intel server generations, batching and co-location of inferences can drastically improve latency-bounded throughput, and the diverse composition of recommendation models leads to different optimization strategies.}, keywords = {Recommendation}, url = {https://arxiv.org/abs/1906.03109 https://drive.google.com/file/d/1v5LbaizV4PK1WvroA5DMBtXwDVRONZ4j/view https://drive.google.com/file/d/1WJ32Cdv1qPLxVk2VQC_Dbmh30sUe5Cfe/view}, author = {Udit Gupta and Carole Wu and Xiaodong Wang and Maxim Naumov and Brandon Reagen and David Brooks and Bradford Cottel and Kim Hazelwood and Bill Jia and Hsien-Hsin Lee and Andrey Malevich and Dheevatsa Mudigere and Mikhail Smelyanskiy and Liang Xiong and Xuan Zhang} } @article {hsia2020cross, title = {Cross-Stack Workload Characterization of Deep Recommendation Systems}, journal = {2020 IEEE International Symposium on Workload Characterization (IISWC)}, year = {2020}, abstract = {Deep learning based recommendation systems form the backbone of most personalized cloud services. Though the computer architecture community has recently started to take notice of deep recommendation inference, the resulting solutions have taken wildly different approaches - ranging from near memory processing to at-scale optimizations. To better design future hardware systems for deep recommendation inference, we must first systematically examine and characterize the underlying systems-level impact of design decisions across the different levels of the execution stack. In this paper, we characterize eight industry-representative deep recommendation models at three different levels of the execution stack: algorithms and software, systems platforms, and hardware microarchitectures. Through this cross-stack characterization, we first show that system deployment choices (i.e., CPUs or GPUs, batch size granularity) can give us up to 15x speedup. To better understand the bottlenecks for further optimization, we look at both software operator usage breakdown and CPU frontend and backend microarchitectural inefficiencies. Finally, we model the correlation between key algorithmic model architecture features and hardware bottlenecks, revealing the absence of a single dominant algorithmic component behind each hardware bottleneck.}, url = {https://doi.org/10.48550/arXiv.2010.05037}, author = {Hsia, Samuel and Udit Gupta and Wilkening, Mark and Carole Wu and Gu Wei and David Brooks} } @conference {Gupta2020b, title = {DeepRecSys: A System for Optimizing End-To-End At-scale Neural Recommendation Inference}, year = {2020}, publisher = {The 47th IEEE/ACM International Symposium on Computer Architecture (ISCA 2020)}, organization = {The 47th IEEE/ACM International Symposium on Computer Architecture (ISCA 2020)}, abstract = {Neural personalized recommendation is the corner-stone of a wide collection of cloud services and products, constituting significant compute demand of the cloud infrastructure. Thus, improving the execution efficiency of neural recommendation directly translates into infrastructure capacity saving. In this paper, we devise a novel end-to-end modeling infrastructure, DeepRecInfra, that adopts an algorithm and system co-design methodology to custom-design systems for recommendation use cases. Leveraging the insights from the recommendation characterization, a new dynamic scheduler, DeepRecSched, is proposed to maximize latency-bounded throughput by taking into account characteristics of inference query size and arrival patterns, recommendation model architectures, and underlying hardware systems. By doing so, system throughput is doubled across the eight industry-representative recommendation models. Finally, design, deployment, and evaluation in at-scale production datacenter shows over 30\% latency reduction across a wide variety of recommendation models running on hundreds of machines.}, keywords = {deep learning, Recommendation}, url = {https://conferences.computer.org/isca/pdfs/ISCA2020-4QlDegUf3fKiwUXfV0KdCm/466100a982/466100a982.pdf}, author = {Udit Gupta and Hsia, Samuel and Saraph, Vikram and Xiaodong Wang and Brandon Reagen and Gu-Yeon Wei and Hsien-Hsin S. Lee and Carole-Jean Wu and David Brooks} } @conference {Wang2020, title = {A Systematic Methodology for Analysis of Deep Learning Hardware and Software Platforms}, year = {2020}, publisher = {Third Conference on Machine Learning and Systems (MLSys)}, organization = {Third Conference on Machine Learning and Systems (MLSys)}, abstract = {Training deep learning models is compute-intensive and there is an industry-wide trend towards hardware and software specialization to improve performance. To systematically compare deep learning systems, we introduce a methodology comprised of a set of analysis techniques and parameterized end-to-end models for fully connected, convolutional, and recurrent neural networks. This methodology can be applied to analyze various hardware and software systems, and is intended to complement traditional methods. We demonstrate its utility by comparing two generations of specialized platforms (Google{\textquoteright}s Cloud TPU v2/v3), three heterogeneous platforms (Google TPU, Nvidia GPU, and Intel CPU), and specialized software stacks (TensorFlow and CUDA).}, keywords = {deep learning, DNN benchmarking and characterization, profiling}, url = {https://proceedings.mlsys.org/papers/2020/12}, author = {Wang Yu and Gu Wei and David Brooks} } @article {xi2019smaug, title = {SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads}, journal = {arXiv e-prints}, year = {2019}, abstract = {In recent years, there has been tremendous advances in hardware acceleration of deep neural networks. However, most of the research has focused on optimizing accelerator microarchitecture for higher performance and energy efficiency on a per-layer basis. We find that for overall single-batch inference latency, the accelerator may only make up 25-40\%, with the rest spent on data movement and in the deep learning software framework. Thus far, it has been very difficult to study end-to-end DNN performance during early stage design (before RTL is available) because there are no existing DNN frameworks that support end-to-end simulation with easy custom hardware accelerator integration. To address this gap in research infrastructure, we present SMAUG, the first DNN framework that is purpose-built for simulation of end-to-end deep learning applications. SMAUG offers researchers a wide range of capabilities for evaluating DNN workloads, from diverse network topologies to easy accelerator modeling and SoC integration. To demonstrate the power and value of SMAUG, we present case studies that show how we can optimize overall performance and energy efficiency for up to 1.8-5x speedup over a baseline system, without changing any part of the accelerator microarchitecture, as well as show how SMAUG can tune an SoC for a camera-powered deep learning pipeline.}, url = {https://doi.org/10.48550/arXiv.1912.04481}, author = {Xi Likun and Yao, Yuan and Bhardwaj, Kshitij and Paul Whatmough and Gu Wei and David Brooks} } @article {ma2019binary, title = {A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM}, journal = {arXiv preprint arXiv:1912.00106}, year = {2019}, abstract = {We propose a new algorithm for training neural networks with binary activations and multi-level weights, which enables efficient processing-in-memory circuits with embedded nonvolatile memories (eNVM). Binary activations obviate costly DACs and ADCs. Multi-level weights leverage multi-level eNVM cells. Compared to existing algorithms, our method not only works for feed-forward networks (e.g., fully-connected and convolutional), but also achieves higher accuracy and noise resilience for recurrent networks. In particular, we present an RNN-based trigger-word detection PIM accelerator, with detailed hardware noise models and circuit co-design techniques, and validate our algorithm{\textquoteright}s high inference accuracy and robustness against a variety of real hardware non-idealities.}, url = {https://doi.org/10.48550/arXiv.1912.00106}, author = {Ma, Siming and David Brooks and Gu Wei} } @booklet {Pentecost2019b, title = {CHAMPVis: Comparative Hierarchical Analysis of Microarchitectural Performance}, howpublished = {ProTools workshop co-located with Supercomputing}, year = {2019}, abstract = {Performance analysis and optimization are essential tasks for hardware and software engineers. In the age of datacenter-scale computing, it is particularly important to conduct comparative performance analysis to understand discrepancies and limitations among different hardware systems and applications. However, there is a distinct lack of productive visualization tools for these comparisons. We present CHAMPVis [1], a web-based, interactive visualization tool that leverages the hierarchical organization of hardware systems to enable productive performance analysis. With CHAMPVis, users can make definitive performance comparisons across applications or hardware platforms. In addition, CHAMPVis provides methods to rank and cluster based on performance metrics to identify common optimization opportunities. Our thorough task analysis reveals three types of datacenter-scale performance analysis tasks: summarization, detailed comparative analysis, and interactive performance bottleneck identification. We propose techniques for each class of tasks including (1) 1-D feature space projection for similarity analysis; (2) Hierarchical parallel coordinates for comparative analysis; and (3) User interactions for rapid diagnostic queries to identify optimization targets. We evaluate CHAMPVis by analyzing standard datacenter applications and machine learning benchmarks in two different case studies.}, keywords = {deep learning, DNN benchmarking and characterization, profiling}, url = {https://doi.org/10.1109/ProTools49597.2019.00013}, author = {Lillian Pentecost and Udit Gupta and Ngan, Elisa and Gu Wei and David Brooks and Beyer, Johanna and Behrisch, Michael} } @article {Donato2019, title = {MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge}, journal = {IEEE MICRO}, volume = {39}, year = {2019}, abstract = {The combination of specialized hardware and embedded nonvolatile memories (eNVM) holds promise for energy-efficient deep neural network (DNN) inference at the edge. However, integrating DNN hardware accelerators with eNVMs still presents several challenges. Multilevel programming is desirable for achieving maximal storage density on chip, but the stochastic nature of eNVM writes makes them prone to errors and further increases the write energy and latency. In this article, we present MEMTI, a memory architecture that leverages a multitask learning technique for maximal reuse of DNN parameters across multiple visual tasks. We show that by retraining and updating only 10\% of all DNN parameters, we can achieve efficient model adaptation across a variety of visual inference tasks. The system performance is evaluated by integrating the memory with the open-source NVIDIA deep learning architecture.}, keywords = {accelerators, deep learning, neural network accelerators}, url = {https://ieeexplore.ieee.org/document/8859219}, author = {Marco Donato and Lillian Pentecost and David Brooks and Gu Wei} } @article {mattson2019mlperf, title = {Mlperf training benchmark}, journal = {arXiv preprint arXiv:1910.01500}, year = {2019}, abstract = {Machine learning (ML) needs industry-standard performance benchmarks to support design and competitive evaluation of the many emerging software and hardware solutions for ML. But ML training presents three unique benchmarking challenges absent from other domains: optimizations that improve training throughput can increase the time to solution, training is stochastic and time to solution exhibits high variance, and software and hardware systems are so diverse that fair benchmarking with the same binary, code, and even hyperparameters is difficult. We therefore present MLPerf, an ML benchmark that overcomes these challenges. Our analysis quantitatively evaluates MLPerf{\textquoteright}s efficacy at driving performance and scalability improvements across two rounds of results from multiple vendors.}, url = {https://doi.org/10.48550/arXiv.1910.01500}, author = {Mattson, Peter and Cheng, Christine and Coleman, Cody and Diamos, Greg and Micikevicius, Paulius and Patterson, David and Tang, Hanlin and Gu Wei and Peter Bailis and Bittorf, Victor and David Brooks and Dehao Chen and Debo Dutta and Udit Gupta and Kim Hazelwood and Andy Hock and Xinyuan Huang and Daniel Kang and Kanter, David and Naveen Kumar and Jeffery Liao and Deepak Narayanan and Tayo Oguntebi and Gennady Pekhimenko and Lillian Pentecost and Vijay Janapa Reddi and Taylor Robie and Tom St John and Carole-Jean Wu and Lingjie Xu and Cliff Young and Matei Zaharia} } @conference {Pentecost2019, title = {MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation}, booktitle = {MICRO {\textquoteright}52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture}, year = {2019}, pages = {769{\textendash}781}, abstract = {Deeply embedded applications require low-power, low-cost hardware that fits within stringent area constraints. Deep learning has many potential uses in these domains, but introduces significant inefficiencies stemming from off-chip DRAM accesses of model weights. Ideally, models would fit entirely on-chip. However, even with compression, memory requirements for state-of-the-art mod- els make on-chip inference impractical. Due to increased density, emerging eNVMs are one promising solution. We present MaxNVM, a principled co-design of sparse encodings, protective logic, and fault-prone MLC eNVM technologies (i.e.,RRAM and CTT) to enable highly-efficient DNN inference. We find bit reduction techniques (e.g., clustering and sparse compression) increase weight vulnerability to faults. This limits the capabilities of MLC eNVM. To circumvent this limitation, we improve storage den- sity (i.e., bits-per-cell) with minimal overhead using protective logic. Tradeoffs between density and reliability result in a rich design space. We show that by balancing these techniques, the weights of large networks are able to reasonably fit on-chip. Compared to a naive, single-level-cell eNVM solution, our highly-optimized MLC memory systems reduce weight area by up to 29{\texttimes}. We compare our technique against NVDLA, a state-of-the-art industry-grade CNN accelerator, and demonstrate up to 3.2{\texttimes} reduced power and up to 3.5{\texttimes} reduced energy per ResNet50 inference.}, keywords = {deep learning, hardware support for machine learning, machine learning, neural network accelerators}, isbn = {978-1-4503-6938-1/19/10}, url = {https://doi.org/10.1145/3352460.3358258}, author = {Lillian Pentecost and Marco Donato and Brandon Reagen and Udit Gupta and Ma, Siming and Gu Wei and David Brooks} } @conference {Plancher2019, title = {Application of Approximate Matrix Multiplication to Neural Networks and Distributed SLAM}, booktitle = {IEEE High Performance Extreme Computing Conference (HPEC)}, year = {2019}, address = {Waltham, MA, USA}, abstract = {Computational efficiency is a critical constraint for a variety of cutting-edge real-time applications. In this work, we identify an opportunity to speed up the end-to-end runtime of two such compute bound applications by incorporating approximate linear algebra techniques. Particularly, we apply approximate matrix multiplication to artificial Neural Networks (NNs) for image classification and to the robotics problem of Distributed Simultaneous Localization and Mapping (DSLAM). Expanding upon recent sampling-based Monte Carlo approximation strategies for matrix multiplication, we develop updated theoretical bounds, and an adaptive error prediction strategy. We then apply these techniques in the context of NNs and DSLAM increasing the speed of both applications by 15-20\% while maintaining a 97\% classification accuracy for NNs running on the MNIST dataset and keeping the average robot position error under 1 meter (vs 0.32 meters for the exact solution). However, both applications experience variance in their results. This suggests that Monte Carlo matrix multiplication may be an effective technique to reduce the memory and computational burden of certain algorithms when used carefully, but more research is needed before these techniques can be widely used in practice.}, keywords = {deep learning, profiling}, url = {https://doi.org/10.1109/HPEC.2019.8916468}, author = {Brian Plancher and Camelia Brumar and Iulian Brumar and Lillian Pentecost and Saketh Rama and David Brooks} } @article {bhardwaj2019determining, title = {Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization}, journal = {IEEE Computer Architecture Letters}, volume = {18}, year = {2019}, pages = {119{\textendash}123}, publisher = {IEEE}, abstract = {The modern system-on-chip (SoC) of the current exascale computing era is complex. These SoCs not only consist of several general-purpose processing cores but also integrate many specialized hardware accelerators. Three common coherency interfaces are used to integrate the accelerators with the memory hierarchy: non-coherent,coherent with the last-level cache (LLC), and fully-coherent.However, using a single coherence interface for all the accelerators in an SoC can lead to significant overheads: in the non-coherent model, accelerators directly access the main memory, which can have considerable performance penalty; whereas in the LLC-coherent model, the accelerators access the LLC but may suffer from performance bottleneck due to contention between several accelerators; and the fully-coherent model, that relies on private caches, can incur non-trivial power/area overheads. Given the limitations of each of these interfaces, this paper proposes a novel performance-aware hybrid coherency interface, where different accelerators use different coherency models, decided at design time based on the target applications so as to optimize the overall system performance. A new Bayesian optimization based framework is also proposed to determine the optimal hybrid coherency interface, i.e., use machine learning to select the best coherency model for each of the accelerators in the SoC in terms of performance. For image processing and classification workloads, the proposed framework determined that a hybrid interface achieves up to 23 percent better performance compared to the other {\textquoteright}homogeneous{\textquoteleft} interfaces, where all the accelerators use a single coherency model.}, author = {Bhardwaj Kshitij and Havasi Marton and Yao Yuan and David Brooks and Lobato Hern{\'a}ndez and Gu Wei} } @proceedings {Ko2019, title = {Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling}, year = {2019}, address = {Barcelona, Spain}, abstract = {Bayesian models and inference is a class of machine learning that is useful for solving problems where the amount of data is scarce and prior knowledge about the application allows you to draw better conclusions. However, Bayesian models often requires computing high-dimensional integrals and finding the posterior distribution can be intractable. One of the most commonly used approximate methods for Bayesian inference is Gibbs sampling, which is a Markov chain Monte Carlo (MCMC) technique to estimate target stationary distribution. The idea in Gibbs sampling is to generate posterior samples by iterating through each of the variables to sample from its conditional given all the other variables fixed. While Gibbs sampling is a popular method for probabilistic graphical models such as Markov Random Field (MRF), the plain algorithm is slow as it goes through each of the variables sequentially. In this work, we describe a binary label MRF Gibbs sampling inference architecture and extend it to 64-label version capable of running multiple perceptual applications, such as sound source separation and stereo matching. The described accelerator employs a chromatic scheduling of variables to parallelize all the conditionally independent variables to 257 samplers, imple- mented on the FPGA portion of a CPU-FPGA SoC. For real-time streaming sound source separation task, we show the hybrid CPU- FPGA implementation is 230x faster than a commercial mobile processor, while maintaining a recommended latency under 50 ms. The 64-label version showed 137x and 679x speedups for binary label MRF Gibbs sampling inference and 64 labels, respectively.}, keywords = {accelerators, bayesian, bayesian inference}, url = {https://doi.org/10.1109/FPL.2019.00033}, author = {Ko, Glenn and Chai, Yuji and Rob Rutenbar and David Brooks and Gu Wei} } @article {tambe2019adaptivfloat, title = {AdaptivFloat: A Floating-Point Based Data Type for Resilient Deep Learning Inference}, journal = {arXiv preprint arXiv:1909.13271}, year = {2019}, abstract = {Conventional hardware-friendly quantization methods, such as fixed-point or integer, tend to perform poorly at very low word sizes as their shrinking dynamic ranges cannot adequately capture the wide data distributions commonly seen in sequence transduction models. We present AdaptivFloat, a floating-point inspired number representation format for deep learning that dynamically maximizes and optimally clips its available dynamic range, at a layer granularity, in order to create faithful encoding of neural network parameters. AdaptivFloat consistently produces higher inference accuracies compared to block floating-point, uniform, IEEE-like float or posit encodings at very low precision (<= 8-bit) across a diverse set of state-of-the-art neural network topologies. And notably, AdaptivFloat is seen surpassing baseline FP32 performance by up to +0.3 in BLEU score and -0.75 in word error rate at weight bit widths that are <= 8-bit. Experimental results on a deep neural network (DNN) hardware accelerator, exploiting AdaptivFloat logic in its computational datapath, demonstrate per-operation energy and area that is 0.9{\texttimes} and 1.14{\texttimes}, respectively, that of equivalent bit width integer-based accelerator variants.}, url = {https://doi.org/10.48550/arXiv.1909.13271}, author = {Tambe, Thierry and Yang,Yu and Wan, Zishen and Deng, Yuntian and Vijay Reddi and Rush, Alexander and David Brooks and Gu Wei} } @conference {Gupta2019, title = {MASR: A Modular Accelerator for Sparse RNNs}, booktitle = {International Conference on Parallel Architectures and Compilation Techniques}, year = {2019}, abstract = {Recurrent neural networks (RNNs) are becoming the de facto solution for speech recognition. RNNs exploit long-term temporal relationships in data by applying repeated, learned transformations. Unlike fully-connected (FC) layers with single vector matrix operations, RNN layers consist of hundreds of such operations chained over time. This poses challenges unique to RNNs that are not found in convolutional neural networks (CNNs) or FC models, namely large dynamic activation. In this paper we present MASR, a principled and modular architecture that accelerates bidirectional RNNs for on-chip ASR. MASR is designed to exploit sparsity in both dynamic activations and static weights. The architecture is enhanced by a series of dynamic activation optimizations that enable compact storage, ensure no energy is wasted computing null operations, and maintain high MAC utilization for highly parallel accelerator designs. In comparison to current state-of-the-art sparse neural network accelerators (e.g., EIE), MASR provides 2x area 3x energy, and 1.6x performance benefits. The modular nature of MASR enables designs that efficiently scale from resource-constrained low-power IoT applications to large-scale, highly parallel datacenter deployments.}, keywords = {accelerators, compression, hardware software co-design, hardware support for machine learning, neural network accelerators}, url = {https://doi.org/10.48550/arXiv.1908.08976}, author = {Udit Gupta and Brandon Reagen and Lillian Pentecost and Marco Donato and Tambe, Thierry and Rush, Alexander and Gu Wei and David Brooks} } @article {wang2019benchmarking, title = {Benchmarking TPU, GPU, and CPU platforms for deep learning}, journal = {arXiv preprint arXiv:1907.10701}, year = {2019}, abstract = {Training deep learning models is compute-intensive and there is an industry-wide trend towards hardware specialization to improve performance. To systematically benchmark deep learning platforms, we introduce ParaDnn, a parameterized benchmark suite for deep learning that generates end-to-end models for fully connected (FC), convolutional (CNN), and recurrent (RNN) neural networks. Along with six real-world models, we benchmark Google{\textquoteright}s Cloud TPU v2/v3, NVIDIA{\textquoteright}s V100 GPU, and an Intel Skylake CPU platform. We take a deep dive into TPU architecture, reveal its bottlenecks, and highlight valuable lessons learned for future specialized system design. We also provide a thorough comparison of the platforms and find that each has unique strengths for some types of models. Finally, we quantify the rapid performance improvements that specialized software stacks provide for the TPU and GPU platforms.}, url = {https://doi.org/10.48550/arXiv.1907.10701}, author = {Wang, Yu and Gu Wei and David Brooks} } @article {ma2019fully, title = {Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights}, journal = {IEEE Electron Device Letters}, volume = {40}, year = {2019}, pages = {1403{\textendash}1406}, publisher = {IEEE}, abstract = {We present a fully CMOS-compatible multilevel non-volatile memory technology, without any special process cost. It is especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency. We use hot carrier injection to program the single-transistor cells, and we conduct charge pumping experiments which identify interfacial traps, rather than bulk oxide traps, as the dominant factor in producing stable I-V shifts. We also derive a new physics-based experimentally verified logarithmic model to explain the rate of interfacial trap generation in large I-V shift regimes where the conventional power-law no longer applies. We fabricate two chips, one using TSMC{\textquoteright}s 16 nm FinFET and the other in 28 nm planar, and show the FinFET cells are more favorable for non-volatile memory due to their better channel control. We store multiple levels in each FinFET cell using a {\textquotedblleft}program and check{\textquotedblright} strategy which sets memory cells{\textquoteright} currents with standard deviations less than 2 μA across a shifting range of over 100 μA. We demonstrate 8 level FinFET cells with extrapolated 10-year charge loss within 10\% at 125 {\textdegree}C.}, url = {https://doi.org/10.1109/LED.2019.2930212}, author = {Ma, Siming and Marco Donato and Sae Lee and David Brooks and Gu Wei} } @article {Lee2019, title = {A 16-nm always-on DNN processor with adaptive clocking and multi-cycle banked SRAMs}, journal = {IEEE Journal of Solid-State Circuits}, volume = {54}, year = {2019}, pages = {1982 - 1992}, abstract = {Always-on subsystems in mobile/Internet of Things (IoT) SoCs process a variety of real-time sensor data deep neural network (DNN) classification workloads in a heavily constrained energy budget. This can be achieved with robust, low-voltage circuits, and specialized hardware accelerators. We present a 16-nm always-on DNN processor, which consists primarily of a microcontroller and a DNN accelerator with on-chip SRAM for the model weights. The design operates robustly from 0.4 to 1-V, with calibration-free automatic voltage/frequency tuning provided by tracking small non-zero razor timing error rates. A novel timing error-driven synchronization-free adaptive clocking scheme significantly reduces the adaptation latency to provide resilience to fast on-chip supply noise and reduce margins. To accommodate the tight energy constraints of always-on IoT workloads, we implement a multi-cycle SRAM read scheme that allows the memory voltage to scale at iso-throughput, improving energy efficiency across the entire operating range. The wide operating range allows for high performance at 1.36 GHz, low-power consumption downs to 750 μW, and stateof-the-art raw efficiency at 16-bit precision of 750 GOPS/W dense or 1.81 TOPS/W sparse.}, keywords = {accelerators, deep learning}, url = {https://ieeexplore.ieee.org/document/8715387}, author = {Sae Lee and Paul Whatmough and David Brooks and Gu Wei} } @article {Whatmough2019, title = {A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators}, journal = {Symposium on VLSI Circuits}, year = {2019}, abstract = {This paper presents a 25mm^2 SoC in 16nm FinFET technology targeting flexible acceleration of compute intensive kernels in DNN, DSP and security algorithms. The SoC includes an always-on sub-system, a dual-core Arm A53 CPU cluster, an embedded FPGA array, and a quad-core cache-coherent accelerator cluster. Measurement results demonstrate the following observations: 1) moving DSP/cryptography kernels from A53 to eFPGA increases energy efficiency between 5.5{\texttimes} - 28.9{\texttimes}, 2) the use of cache coherency for datapath accelerators increases throughput by 2.94{\texttimes}, and 3) accelerator flexibility-efficiency (GOPS/W) range spans from 3.1{\texttimes} (A53+S1MD), to 16.5{\texttimes} (eFPGA), to 54.5{\texttimes} (CCA) compared to the dual-core CPU baseline on comparable tasks. The energy per inference on MobileNet-128 CNN shows a peak improvement of 47.6{\texttimes}.}, keywords = {deep learning, hardware support for machine learning, machine learning, neural network accelerators}, url = {https://ieeexplore.ieee.org/abstract/document/8778002/authors$\#$authors}, author = {Paul Whatmough and Sae Lee and Marco Donato and Hsea Hsueh and Sam Xi and Udit Gupta and Lillian Pentecost and Ko, Glenn and David Brooks and Gu Wei} } @conference {ko2019flexgibbs, title = {Flexgibbs: Reconfigurable parallel gibbs sampling accelerator for structured graphs}, booktitle = {2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, year = {2019}, pages = {334{\textendash}334}, abstract = {Many consider one of the key components to the success of deep learning as its compatibility with existing accelerators, mainly GPU. While GPUs are great at handling linear algebra kernels commonly found in deep learning, they are not the optimal architecture for handling unsupervised learning methods such as Bayesian models and inference. As a step towards, achieving better understanding of architectures for probabilistic models, Gibbs sampling, one of the most commonly used algorithms for Bayesian inference, is studied with a focus on parallelism that converges to the target distribution and parameterized components. We propose FlexGibbs, a reconfigurable parallel Gibbs sampling inference accelerator for structured graphs. We designed an architecture optimal for solving Markov Random Field tasks using an array of parallel Gibbs samplers, enabled by chromatic scheduling. We show that for sound source separation application, FlexGibbs configured on the FPGA fabric of Xilinx Zync CPU-FPGA SoC achieved Gibbs sampling inference speedup of 1048x and 99.85\% reduction in energy over running it on ARM Cortex-A53.}, url = {https://doi.org/10.1109/FCCM.2019.00075}, author = {Ko, G and Chai, Yuji and Rutenbar, A and David Brooks and Gu Wei} } @proceedings {wangispass2019, title = {Demystifying Bayesian Inference Workloads}, year = {2019}, abstract = {The recent surge of machine learning has motivated computer architects to focus intently on accelerating related workloads, especially in deep learning. Deep learning has been the pillar algorithm that has led the advancement of learning patterns from a vast amount of labeled data, or supervised learning. However, for unsupervised learning, Bayesian methods often work better than deep learning. Bayesian modeling and inference works well with unlabeled or limited data, can leverage informative priors, and has interpretable models. Despite being an important branch of machine learning, Bayesian inference generally has been overlooked by the architecture and systems communities. In this paper, we facilitate the study of Bayesian inference with the development of BayesSuite, a collection of seminal Bayesian inference workloads. We characterize the power and performance profiles of BayesSuite across a variety of current-generation processors and find significant diversity. Manually tuning and deploying Bayesian inference workloads requires deep understanding of the workload characteristics and hardware specifications. To address these challenges and provide high-performance, energy-efficient support for Bayesian infer- ence, we introduce a scheduling and optimization mechanism that can be plugged into a system scheduler. We also propose a computation elision technique that further improves the performance and energy efficiency of the workloads by skipping computations that do not improve the quality of the inference. Our proposed techniques are able to increase Bayesian inference performance by 5.8{\texttimes} on average over the naive assignment and execution of the workloads.}, keywords = {bayesian inference, profiling, workload characterization}, url = {https://doi.org/10.1109/ISPASS.2019.00031}, author = {Yu Emma Wang and Yuhao Zhu and Ko, Glenn and Brandon Reagen and Gu-Wei and David Brooks} } @article {wangtaco2019, title = {Predicting New Workload or CPU Performance by Analyzing Public Datasets}, journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, volume = {15}, year = {2019}, pages = {53:1{\textendash}53:21}, abstract = {The marketplace for general-purpose microprocessors offers hundreds of functionally similar models, differing by traits like frequency, core count, cache size, memory bandwidth, and power consumption. Their performance depends not only on microarchitecture, but also on the nature of the workloads being executed. Given a set of intended workloads, the consumer needs both performance and price information to make rational buying decisions. Many benchmark suites have been developed to measure processor performance, and their results for large collections of CPUs are often publicly available. However, repositories of benchmark results are not always helpful when consumers need performance data for new processors or new workloads. Moreover, the aggregate scores for benchmark suites designed to cover a broad spectrum of workload types can be misleading. To address these problems, we have developed a deep neural network (DNN) model, and we have used it to learn the relationship between the specifications of Intel CPUs and their performance on the SPEC CPU2006 and Geekbench 3 benchmark suites. We show that we can generate useful predictions for new processors and new workloads. We also cross-predict the two benchmark suites and compare their performance scores. The results quantify the self-similarity of these suites for the first time in the literature. This work should discourage consumers from basing purchasing decisions exclusively on Geekbench 3, and it should encourage academics to evaluate research using more diverse workloads than the SPEC CPU suites alone.}, keywords = {cpu, performance prediction}, url = {https://yuemmawang.github.io/publications/wang-taco2019.pdf}, author = {Wang, Yu and Victor Lee and Gu Wei and David Brooks} } @booklet {wei2019capacitor, title = {Capacitor reconfiguration of a single-input, multi-output, switched-capacitor converter}, year = {2019}, note = {US Patent 10,250,130}, author = {Gu Wei and Tao Tong and David Brooks and Sae Lee} } @patent {wei2019device, title = {Device and method for hybrid feedback control of a switch-capacitor multi-unit voltage regulator}, year = {2019}, note = {US Patent 10,199,931}, edition = {United States of America}, chapter = {US}, abstract = {

A device and method for hybrid feedback control of a switch-capacitor multi-unit voltage regulator are presented. A multi-unit switched-capacitor (SC) core includes a plurality of SC converter units, each unit with a capacitor and a plurality of switches controllable by a plurality of switching signals. Power switch drivers provide a switching signal to each SC converter unit. A secondary proactive loop circuit includes a feedback control circuit configured to control one or more of the plurality of switches. A comparator is configured to compare the regulator output voltage with a reference voltage and provide a comparator trigger signal. Ripple reduction logic is configured to receive the comparator trigger signal and provide an SC unit allocation signal. A multiplexer is configured to receive a first clock signal, a second clock signal, and the SC unit allocation signal and provide a signal to the power switch drivers.

}, url = {https://patents.justia.com/patent/10199931}, author = {Gu Wei and Tao Tong and David Brooks and Sae Lee} } @conference {Reagen2017b, title = {Weightless: Lossy Weight Encoding For Deep Neural Network Compression}, booktitle = {International Conference on Machine Learning}, year = {2018}, pages = {4324{\textendash}4333}, abstract = {The large memory requirements of deep neural networks limit their deployment and adoption on many devices. Model compression methods effectively reduce the memory requirements of these models, usually through applying transformations such as weight pruning or quantization. In this paper, we present a novel scheme for lossy weight encoding which complements conventional compression techniques. The encoding is based on the Bloomier filter, a probabilistic data structure that can save space at the cost of introducing random errors. Leveraging the ability of neural networks to tolerate these imperfections and by re-training around the errors, the proposed technique, Weightless, can compress DNN weights by up to 496x with the same model accuracy. This results in up to a 1.51x improvement over the state-of-the-art.}, keywords = {compression, deep learning}, url = {https://arxiv.org/abs/1711.04686}, author = {Brandon Reagen and Udit Gupta and Robert Adolf and Mitzenmacher, Michael and Rush, Alexander and Gu Wei and David Brooks} } @article {Lee2018, title = {A wide dynamic range sparse FC-DNN processor with multi-cycle banked SRAM read and adaptive clocking in 16nm FinFET}, journal = {ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference}, year = {2018}, abstract = {Always-on classifiers for sensor data require a very wide operating range to support a variety of real-time workloads and must operate robustly at low supply voltages. We present a 16nm always-on wake-up controller with a fully-connected (FC) Deep Neural Network (DNN) accelerator that operates from 0.4-1 V. Calibration-free automatic voltage/frequency tuning is provided by tracking small non-zero Razor timing-error rates, and a novel timing-error driven sync-free fast adaptive clocking scheme provides resilience to on-chip supply voltage noise. The model access burden of neural networks is relaxed using a multicycle SRAM read, which allows memory voltage to be reduced at iso-throughput. The wide operating range allows for high performance at 1.36GHz, low-power consumption down to 750μW and state-of-the-art raw efficiency at 16-bit precision of 750 GOPS/W dense, or 1.81 TOPS/W sparse.}, keywords = {accelerators, deep learning}, url = {https://ieeexplore.ieee.org/abstract/document/8494245}, author = {Sae Lee and Paul Whatmough and Niamh Mulholland and Patrick Hansen and David Brooks and Gu Wei} } @article {garibotti2018assisting, title = {Assisting high-level synthesis improve spmv benchmark through dynamic dependence analysis}, journal = {IEEE Transactions on Circuits and Systems II: Express Briefs}, volume = {65}, year = {2018}, pages = {1440{\textendash}1444}, publisher = {IEEE}, abstract = {Recent advances in high-level synthesis (HLS) have enabled an automatic means of generating register-transfer level from high-level specifications without compromising performance. HLS provides substantial improvements to productivity and is a promising solution to designing future heterogeneous chips consisting of dozens of unique IP blocks (i.e., hardware accelerators). Despite their impressive capabilities, HLS tools today are commonly used to target a small subset of workloads, i.e., ones with inordinately regular control flow and memory access patterns. The challenges of achieving high-quality hardware for irregular workloads stems from HLS relying on static analysis. Static analysis is overly conservative when dealing with non-uniform memory access and imbalanced workloads, and identifying the most appropriate parallelizing strategy. In this brief, we propose the use of dynamic analysis to generate higher quality designs using commercial HLS tools. Our evaluations show that with dynamic dependence analysis, HLS designs achieve 3.3{\texttimes} performance improvement for the sparse matrix-vector multiply benchmark.}, url = {https://doi.org/10.1109/TCSII.2018.2860122}, author = {Garibotti, Rafael and Brandon Reagen and Yakun Shao and Gu Wei and David Brooks} } @article {Whatmough2018b, title = {SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devices}, journal = {Hot Chips 30: A Symposium on High Performance Chips}, volume = {99}, year = {2018}, pages = {1-1}, abstract = {Emerging Internet of Things (IoT) devices necessitate system-on-chips (SoCs) that can scale from ultralow power always-on (AON) operation, all the way up to less frequent high-performance tasks at high energy efficiency. Specialized accelerators are essential to help meet these needs at both ends of the scale, but maintaining workload flexibility remains an important goal. This article presents a 25-mm{\texttwosuperior} SoC in 16-nm FinFET technology which demonstrates targeted, flexible acceleration of key compute-intensive kernels spanning machine learning (ML), DSP, and cryptography. The SMIV SoC includes a dedicated AON sub-system, a dual-core Arm Cortex-A53 CPU cluster, an SoC-attached embedded field-programmable gate array (eFPGA) array, and a quad-core cache-coherent accelerator (CCA) cluster. Measurement results demonstrate: 1) 1236x power envelope, from 1.1 mW (only AON cluster), up to 1.36 W (whole SoC at maximum throughput); 2) 5.5-28.9x energy efficiency gain from offloading compute kernels from A53 to eFPGA; 3) 2.94x latency improvement using coherent memory access (CCA cluster); and 4) 55x MobileNetV1 energy per inference improvement on CCA compared to the CPU baseline. The overall flexibility-efficiency range on SMIV spans measured energy efficiencies of 1x (dual-core A53), 3.1x (A53 with SIMD), 16.5x (eFPGA), 54.9x (CCA), and 256x (AON) at a peak efficiency of 4.8 TOPS/W.}, keywords = {accelerators, deep learning}, url = {http://dx.doi.org/10.1109/JSSC.2021.3115466}, author = {Paul Whatmough and Sae Lee and Sam Xi and Udit Gupta and Lillian Pentecost and Marco Donato and Hsea Hseuh and David Brooks and Gu Wei} } @article {Whatmough2018, title = {DNN ENGINE: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications}, journal = {IEEE Journal of Solid-State Circuits (JSSC)}, volume = {53}, year = {2018}, abstract = {This paper presents a 28-nm system-on-chip (SoC) for Internet of things (IoT) applications with a programmable accelerator design that implements a powerful fully connected deep neural network (DNN) classifier. To reach the required low energy consumption, we exploit the key properties of neural network algorithms: parallelism, data reuse, small/sparse data, and noise tolerance. We map the algorithm to a very large scale integration (VLSI) architecture based around an singleinstruction, multiple-data data path with hardware support to exploit data sparsity by completely eliding unnecessary computation and data movement. This approach exploits sparsity, without compromising the parallel computation. We also exploit the inherent algorithmic noise-tolerance of neural networks, by introducing circuit-level timing violation detection to allow worst case voltage guard-bands to be minimized. The resulting intermittent timing violations may result in logic errors, which conventionally need to be corrected. However, in lieu of explicit error correction, we cope with this by accentuating the noise tolerance of neural networks. The measured test chip achieves high classification accuracy (98.36\% for the MNIST test set), while tolerating aggregate timing violation rates\>10 -1 . The accelerator achieves a minimum energy of 0.36 μJ/inference at 667 MHz; maximum throughput at 1.2 GHz and 0.57 μJ/inference; or a 10\% margined operating point at 1 GHz and 0.58 μJ/inference.}, keywords = {accelerators, deep learning}, url = {https://doi.org/10.1109/JSSC.2018.2841824}, author = {Paul Whatmough and Sae Lee and David Brooks and Gu Wei} } @conference {donato2018chip, title = {On-chip deep neural network storage with multi-level eNVM}, booktitle = {DAC {\textquoteright}18: Proceedings of the 55th Annual Design Automation Conference}, year = {2018}, pages = {1{\textendash}6}, address = {San Francisco, CA, USA}, abstract = {

One of the biggest performance bottlenecks of today{\textquoteright}s neural network (NN) accelerators is off-chip memory accesses [11]. In this paper, we propose a method to use multi-level, embedded nonvolatile memory (eNVM) to eliminate all off-chip weight accesses. The use of multi-level memory cells increases the probability of faults. Therefore, we co-design the weights and memories such that their properties complement each other and the faults result in no noticeable NN accuracy loss. In the extreme case, the weights in fully connected layers can be stored using a single transistor. With weight pruning and clustering, we show our technique reduces the memory area by over an order of magnitude compared to an SRAM baseline. In the case of VGG16 (130M weights), we are able to store all the weights in 4.9 mm2, well within the area allocated to SRAM in modern NN accelerators [6]

}, url = {https://doi.org/10.1145/3195970.3196083}, author = {Marco Donato and Brandon Reagen and Lillian Pentecost and Udit Gupta and David Brooks and Gu Wei} } @conference {Reagen2018, title = {Ares: a framework for quantifying the resilience of deep neural networks}, booktitle = {Design Automation Conference}, volume = {17}, year = {2018}, pages = {1-6}, abstract = {As the use of deep neural networks continues to grow, so does the fraction of compute cycles devoted to their execution. This has led the CAD and architecture communities to devote considerable attention to building DNN hardware. Despite these efforts, the fault tolerance of DNNs has generally been overlooked. This paper is the first to conduct a large-scale, empirical study of DNN resilience. Motivated by the inherent algorithmic resilience of DNNs, we are interested in understanding the relationship between fault rate and model accuracy. To do so, we present Ares: a light-weight, DNN-specific fault injection framework validated within 12\% of real hardware. We find that DNN fault tolerance varies by orders of magnitude with respect to model, layer type, and structure.}, keywords = {deep learning, dnn, fault tolerance, reliability}, url = {https://dl.acm.org/citation.cfm?id=3195997}, author = {Brandon Reagen and Udit Gupta and Lillian Pentecost and Paul Whatmough and Sae Lee and Niamh Mulholland and David Brooks and Gu Wei} } @conference {Donato2018, title = {On-Chip Deep Neural Network Storage with Multi-Level eNVM}, booktitle = {Design Automation Conference (DAC)}, year = {2018}, abstract = {One of the biggest performance bottlenecks of today{\textquoteright}s neural network (NN) accelerators is off-chip memory accesses. In this paper, we propose a method to use multi-level, embedded non-volatile memory (eNVM) to eliminate all off-chip weight accesses. The use of multi-level memory cells increases the probability of faults. Therefore, we co-design the weights and memories such that their properties complement each other and the faults result in no noticeable NN accuracy loss. In the extreme case, the weights in fully connected layers can be stored using a single transistor. With weight pruning and clustering, we show our technique reduces the memory area by over an order of magnitude compared to an SRAM baseline. In the case of VGG16 (130M weights), we are able to store all the weights in 4.9 mm2, well within the area allocated to SRAM in modern NN accelerators.}, keywords = {deep learning, dnn}, url = {https://doi.org/10.1109/DAC.2018.8465818}, author = {Marco Donato and Brandon Reagen and Lillian Pentecost and Udit Gupta and David Brooks and Gu Wei} } @article {Lok2018, title = {A Low Mass Power Electronics Unit to Drive Piezoelectric Actuators for Flying Microrobots}, journal = {IEEE Transactions on Power Electronics}, volume = {33}, year = {2018}, pages = {3180 - 3191}, abstract = {This paper presents a power electronics design for the piezoelectric actuators of an insect-scale flapping-wing robot, the RoboBee. The proposed design outputs four high-voltage drive signals tailored for the two bimorph actuators of the RoboBee in an alternating drive configuration. It utilizes fully integrated drive stage circuits with a novel highside gate driver to save chip area and meet the strict mass constraint of the RoboBee. Compared with previous integrated designs, it also boosts efficiency in delivering energy to the actuators and recovering unused energy by applying three power saving techniques, dynamic common mode adjustment, envelope tracking, and charge sharing. Using this design to energize four 15 nF capacitor loads with a 200 V and 100 Hz drive signal and tracking the control commands recorded from an actual flight experiment for the robot, we measure an average power consumption of 290 mW.}, keywords = {robobees}, url = {https://doi.org/10.1109/TPEL.2017.2704290}, author = {Mario Lok and Elizabeth Farrell Helbling and Xuan Zhang and Robert Wood and David Brooks and Gu Wei} } @article {zhu2018cloud, title = {Cloud no longer a silver bullet, edge to the rescue}, journal = {arXiv preprint arXiv:1802.05943}, year = {2018}, abstract = {This paper takes the position that, while cognitive computing today relies heavily on the cloud, we will soon see a paradigm shift where cognitive computing primarily happens on network edges. The shift toward edge devices is fundamentally propelled both by technological constraints in data centers and wireless network infrastructures, as well as practical considerations such as privacy and safety. The remainder of this paper lays out our view of how these constraints will impact future cognitive computing. Bringing cognitive computing to edge devices opens up several new opportunities and challenges, some of which demand new solutions and some of which require us to revisit entrenched techniques in light of new technologies. We close the paper with a call to action for future research.}, url = {https://doi.org/10.48550/arXiv.1802.05943}, author = {Yuhao Zhu and Gu Wei and David Brooks} } @article {campanoni2017automatically, title = {Automatically accelerating non-numerical programs by architecture-compiler co-design}, journal = {Communications of the ACM}, volume = {60}, year = {2017}, pages = {88{\textendash}97}, publisher = {ACM}, abstract = {Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from thread execution in conventional multicore architecures. Simulations of HELIX-RC, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85{\texttimes} performance speedup for six SPEC CINT2000 benchmarks.}, url = {https://dl.acm.org/doi/10.1145/3139461}, author = {Simone Campanoni and Kevin Brownell and Svilen Kanev and Timothy Jones and Gu Wei and David Brooks} } @conference {Kodali2017, title = {Applications of Deep Neural Networks for Ultra Low Power IoT}, booktitle = {International Conference on Computer Design}, year = {2017}, abstract = {IoT devices are increasing in prevalence and popularity, becoming an indispensable part of daily life. Despite the stringent energy and computational constraints of IoT systems, specialized hardware can enable energy-efficient sensor-data classification in an increasingly diverse range of IoT applications. This paper demonstrates seven different IoT applications using a fully-connected deep neural network (FC-NN) accelerator on 28nm CMOS. The applications include audio keyword spotting, face recognition, and human activity recognition. For each application, a FC-NN model was trained from a preprocessed dataset and mapped to the accelerator. Experimental results indicate the models retained their state-of-the-art accuracy on the accelerator across a broad range of frequencies and voltages. Real-time energy results for the applications were found to be on the order of 100nJ per inference or lower.}, keywords = {accelerators, dnn, machine learning}, url = {https://doi.org/10.1109/ICCD.2017.102}, author = {Sreela Kodali and Patrick Hansen and Niamh Mulholland and Paul Whatmough and David Brooks and Gu Wei} } @conference {bertran2017very, title = {Very low voltage (VLV) design}, booktitle = {2017 IEEE International Conference on Computer Design (ICCD)}, year = {2017}, pages = {601{\textendash}604}, publisher = {IEEE}, organization = {IEEE}, address = {Boston, MA, USA}, abstract = {This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the performance and system reliability constraints that are key impediments to VLV. The associated trade-offs across power, performance and reliability are helpful in inferring the optimal operational voltage-frequency point. This work was performed under the auspices of an ongoing DARPA program (named PERFECT) that is focused on maximizing system-level energy efficiency.}, url = {https://doi.org/10.1109/ICCD.2017.105}, author = {Bertran, Ramon and Pradip Bose and David Brooks and Burns, Jeff and Alper Buyuktosunoglu and Chandramoorthy, Nandhini and Cheng, Eric and Cochet, Martin and Eldridge, Schuyler and Friedman, Daniel and others} } @conference {Whatmough2017b, title = {Sub-uJ Deep Neural Networks for Embedded Applications}, booktitle = {IEEE 51st Asilomar Conference on Signals, Systems, and Computers}, year = {2017}, address = {Pacific Grove, CA, USA}, abstract = {To intelligently process sensor data on internet of things (IoT) devices, we require powerful classifiers that can operate at sub-uJ energy levels. Previous work has focused on spiking neural network (SNN) algorithms, which are well suited to VLSI implementation due to the single-bit connections between neurons in the network. In contrast, deep neural networks (DNNs) are not as well suited to hardware implementation, because the compute and storage demands are high. In this paper, we demonstrate that there are a variety of optimizations that can be applied to DNNs to reduce the energy consumption such that they outperform SNNs in terms of energy and accuracy. Six optimizations are surveyed and applied to a SIMD accelerator architecture. The accelerator is implemented in a 28nm SoC test chip. Measurement results demonstrate ~10X aggregate improvement in energy efficiency, with a minimum energy of 0.36uJ/inference at 667MHz clock frequency. Compared to previously published spiking neural network accelerators, we demonstrate an improvement in energy efficiency of more than an order of magnitude, across a wide energy-accuracy trade-off range.}, keywords = {accelerators, dnn, iot, machine learning}, url = {https://doi.org/10.1109/ACSSC.2017.8335697}, author = {Paul Whatmough and Sae Lee and Gu Wei and David Brooks} } @article {chaput2017area, title = {An area-efficient 8-bit single-ended ADC with extended input voltage range}, journal = {IEEE Transactions on Circuits and Systems II: Express Briefs}, volume = {65}, year = {2017}, pages = {1549{\textendash}1553}, publisher = {IEEE}, abstract = {This brief presents an 8-bit successive approximation register analog-to-digital converter (ADC) implemented within a system-on-chip (SoC) for autonomous flapping-wing microrobots. The ADC implements hybrid split-capacitor sub-digital-to-analog converter (DAC) techniques to achieve 35.72\% improvement in a capacitor bank energy-area product. The device also implements an extended single-ended input voltage range allowing a direct connection to sensors while maintaining low-power operation. This technique allows 51.7\% DAC switching energy reduction compared to the state of the art. The SoC, fabricated in 40-nm CMOS, includes four parallel 0.001 mm 2 1 MS/s ADC cores multiplexed across 13 input ports. It enables 0 to 1.8-V input range while operating off of a 0.9 V supply. At 1 MS/s, the ADC achieves a signal-to-noise and distortion ratio of 45.6 dB for a 1.6-V pp input signal and consumes 10.4 μW.}, author = {Simon Chaput and David Brooks and Gu Wei} } @conference {reagen2017methods, title = {Methods and infrastructure in the era of accelerator-centric architectures}, booktitle = {2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)}, year = {2017}, pages = {902{\textendash}905}, publisher = {IEEE}, organization = {IEEE}, address = {Boston, MA, USA}, abstract = {Computer architecture today is anything but business as usual, and what is bad for business is often great for science. As Moore{\textquoteright}s Law continues to unwaveringly march forward, despite the ceasing of Dennard scaling, continued performance gains with each processor generation has become a significant challenge, and requires creative solutions. Namely, the way to continue to scale performance in light of power issues is through hardware specialization. Hardware accelerators promise not only orders of magnitude in performance improvements over general purpose processors, but sport similar energy efficiency gains. However, accelerators are equal parts problem solver as they are creator. The major problem is designing and integrating accelerators into a complex environment within the stringent SoC design cycles. Given that each accelerator has a rich design space and convoluted implications and interactions with the memory system, better mechanisms for studying this new-breed of SoC are needed. To usher in the new era of computer architecture, we have built Aladdin: a high-level accelerator simulator enabling rapid accelerator design. Aladdin was recently extended to operate in conjunction with gem5 to study memory system interactions. In this paper we will recount the operation and utilities of Aladdin and gem5-Aladdin, concluding with a case study of how Aladdin can be used to optimize DNN accelerators.}, url = {https://doi.org/10.1109/MWSCAS.2017.8053070}, author = {Brandon Reagen and Yakun Shao and Sam Xi and Gu Wei and David Brooks} } @book {Reagen2017b, title = {Deep Learning for Computer Architects}, series = {Synthesis Lectures on Computer Architecture}, year = {2017}, publisher = {Morgan \& Claypool Publishers}, organization = {Morgan \& Claypool Publishers}, abstract = {Machine learning, and specifically deep learning, has been hugely disruptive in many fields of computer science. The success of deep learning techniques in solving notoriously difficult classification and regression problems has resulted in their rapid adoption in solving real-world problems. The emergence of deep learning is widely attributed to a virtuous cycle whereby fundamental advancements in training deeper models were enabled by the availability of massive datasets and high-performance computer hardware. This text serves as a primer for computer architects in a new and rapidly evolving field. We review how machine learning has evolved since its inception in the 1960s and track the key developments leading up to the emergence of the powerful deep learning techniques that emerged in the last decade. Next we review representative workloads, including the most commonly used datasets and seminal networks across a variety of domains. In addition to discussing the workloads themselves, we also detail the most popular deep learning tools and show how aspiring practitioners can use the tools with the workloads to characterize and optimize DNNs. The remainder of the book is dedicated to the design and optimization of hardware and architectures for machine learning. As high-performance hardware was so instrumental in the success of machine learning becoming a practical solution, this chapter recounts a variety of optimizations proposed recently to further improve future designs. Finally, we present a review of recent research published in the area as well as a taxonomy to help readers understand how various contributions fall in context.}, keywords = {deep learning, DNN benchmarking and characterization, hardware software co-design, hardware support for machine learning, neural network accelerators}, url = {http://www.morganclaypool.com/doi/abs/10.2200/S00783ED1V01Y201706CAC041}, author = {Brandon Reagen and Robert Adolf and Paul Whatmough and Gu-Wei and David Brooks} } @conference {Whatmough2017b, title = {DNN ENGINE: A 16nm Sub-uJ Deep Neural Network Inference Accelerator for the Embedded Masses}, booktitle = {Hot Chips 29: A Symposium on High Performance Chips}, year = {2017}, keywords = {accelerators, dnn, machine learning}, url = {chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/viewer.html?pdfurl=https\%3A\%2F\%2Fold.hotchips.org\%2Fwp-content\%2Fuploads\%2Fhc_archives\%2Fhc29\%2FHC29.22-Tuesday-Pub\%2FHC29.22.70-NeuralNet2-Pub\%2FHC29.22.711-DNN-Engine-Whatmough-ARM-0.6_clean.pdf\&clen=1}, author = {Paul Whatmough and Sae Lee and Niamh Mulholland and Patrick Hansen and Sreela Kodali and David Brooks} } @conference {Reagen2017, title = {A Case for Efficient Accelerator Design Space Exploration via Bayesian Optimization}, booktitle = {International Symposium on Low Power Electronics and Design}, year = {2017}, address = {Taipei, Taiwan}, abstract = {In this paper we propose using machine learning to improve the design of deep neural network hardware accelerators. We show how to adapt multi-objective Bayesian optimization to overcome a challenging design problem: optimizing deep neural network hardware accelerators for both accuracy and energy efficiency. DNN accelerators exhibit all aspects of a challenging optimization space: the landscape is rough, evaluating designs is expensive, the objectives compete with each other, and both design spaces (algorithmic and microarchitectural) are unwieldy. With multi-objective Bayesian optimization, the design space exploration is made tractable and the design points found vastly outperform traditional methods across all metrics of interest.}, keywords = {accelerators, bayesian, machine learning}, url = {https://doi.org/10.1109/ISLPED.2017.8009208}, author = {Brandon Reagen and Jose Hernandez-Lobato and Robert Adolf and Michael Gelbart and Paul Whatmough and Gu Wei and David Brooks} } @conference {zou2017ivory, title = {Ivory: Early-stage design space exploration tool for integrated voltage regulators}, booktitle = {Proceedings of the 54th Annual Design Automation Conference 2017}, year = {2017}, pages = {1{\textendash}6}, address = {Austin, TX}, abstract = {Despite being employed in burgeoning efforts to improve power delivery efficiency, integrated voltage regulators (IVRs) have yet to be evaluated in a rigorous, systematic, or quantitative manner. To fulfill this need, we present Ivory, a high-level design space exploration tool capable of providing accurate conversion efficiency, static performance characteristics, and dynamic transient responses of an IVR-enabled power delivery subsystem (PDS), enabling rapid trade-off exploration at early design stage, approximately 1000{\texttimes} faster than SPICE simulation. We demonstrate and validate Ivory with a wide spectrum of IVR topologies. In addition, we present a case study using Ivory to reveal the optimal PDS configurations, with underlying power break-downs and area overheads for the GPU manycore architecture, which has yet to embrace IVRs.}, url = {https://doi.org/10.1145/3061639.3062268}, author = {Zou, An and Leng, Jingwen and Zu, Yazhou and Tao Tong and Vijay Reddi and David Brooks and Gu Wei and Xuan Zhang} } @article {Zhang2017, title = {A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle}, journal = {IEEE Journal of Solid-State Circuits}, volume = {52}, year = {2017}, pages = {2374 - 2387}, abstract = {We demonstrate a fully integrated system-on-chip (SoC) optimized for insect-scale flapping-wing pico-aerial vehicles. The SoC is able to meet the stringent weight, power, and real-time performance demands of autonomous flight for a bee-sized robot. The entire integrated system with embedded voltage regulation, data conversion, clock generation, as well as both general-purpose and accelerated computing units, weighs less than 3 mg after die thinning. It is self-contained and can be powered directly off of a lithium battery. Measured results show open-loop wing flapping controlled by the SoC and improved energy efficiency through the use of hardware acceleration and supply resilience through the use of adaptive clocking.}, keywords = {robobees}, url = {https://doi.org/10.1109/JSSC.2017.2705170}, author = {Xuan Zhang and Mario Lok and Tao Tong and Sae Lee and Brandon Reagen and Pierre. Duhamel and Robert Wood and David Brooks and Gu Wei} } @conference {garibotti2017using, title = {Using dynamic dependence analysis to improve the quality of high-level synthesis designs}, booktitle = {2017 IEEE International Symposium on Circuits and Systems (ISCAS)}, year = {2017}, pages = {1{\textendash}4}, publisher = {IEEE}, organization = {IEEE}, address = {Baltimore, MD, USA}, abstract = {High-Level Synthesis (HLS) tools that compile algorithms written in high-level languages into register-transfer level implementations can significantly improve design productivity and lower engineering cost. However, HLS-generated designs still lag handwritten implementations in a number of areas, particularly in the efficient allocation of hardware resources. In this work, we propose the use of dynamic dependence analysis to generate higher quality designs using existing HLS tools. We focus on resource sharing for compute-intensive workloads, a major limitation of relying only on static analysis. We demonstrate that with dynamic dependence analysis, the synthesized designs can achieve an order of magnitude resource reduction without performance loss over the state-of-the-art HLS solutions.}, url = {https://doi.org/10.1109/ISCAS.2017.8050748}, author = {Garibotti, Rafael and Brandon Reagen and Yakun Shao and Gu Wei and David Brooks} } @article {Lee2017, title = {A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC{\textendash}DC Converter}, journal = {IEEE Transactions on VLSI}, volume = {25}, year = {2017}, pages = {1271-1284}, abstract = {This paper presents a 16-core voltage-stacked system with adaptive frequency clocking (AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power delivery for multicore systems. Voltage stacking alleviates power delivery inefficiencies due to off-chip parasitics but adds complexity to combat internal voltage noise. To address the corresponding issue of internal voltage noise, the system utilizes an AFClk scheme with an efficient switched-capacitor dc-dc converter to mitigate noise on the stack layers and to improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation as well as the potential of voltage stacking as a highly efficient power delivery scheme. This paper also illustrates that augmenting the hardware techniques with intelligent workload allocation that exploits the inherent properties of voltage stacking can preemptively reduce the interlayer activity mismatch and improve system efficiency.}, keywords = {voltage-regulator, voltage-stacking}, url = {https://www.academia.edu/75987623/A_16_Core_Voltage_Stacked_System_With_Adaptive_Clocking_and_an_Integrated_Switched_Capacitor_DC_DC_Converter}, author = {Sae Kyu Lee and Tao Tong and Xuan Zhang and David Brooks and Gu Wei} } @conference {Kanev2017, title = {Mallacc: Accelerating Memory Allocation}, booktitle = {International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS)}, volume = {5}, year = {2017}, pages = {33-45}, edition = {2}, abstract = {Recent work shows that dynamic memory allocation consumes nearly 7\% of all cycles in Google datacenters. With the trend towards increased specialization of hardware, we propose Mallacc, an in-core hardware accelerator designed for broad use across a number of high-performance, modern memory allocators. The design of Mallacc is quite different from traditional throughput-oriented hardware accelerators. Because memory allocation requests tend to be very frequent, fast, and interspersed inside other application code, accelerators must be optimized for latency rather than throughput and area overheads must be kept to a bare minimum. Mallacc accelerates the three primary operations of a typical memory allocation request: size class computation, retrieval of a free memory block, and sampling of memory usage. Our results show that malloc latency can be reduced by up to 50\% with a hardware cost of less than 1500 μm 2 of silicon area, less than 0.006\% of a typical high-performance processor core.}, keywords = {accelerators, datacenter}, url = {http://dx.doi.org/10.1145/3093315.3037736}, author = {Svilen Kanev and Sam Xi and Gu Wei and David Brooks} } @article {zhu2017cognitive, title = {Cognitive computing safety: The new horizon for reliability}, journal = {IEEE Micro}, volume = {37}, year = {2017}, pages = {15{\textendash}21}, abstract = {This column includes two invited position papers about the challenges and opportunities in cognitive architectures.}, url = {https://doi.org/10.1109/MM.2017.2}, author = {Yuhao Zhu and Vijay Reddi} } @conference {Whatmough2017, title = {A 28nm SoC with a 1.2GHz 568nJ/Prediction Sparse Deep-Neural-Network Engine with \>0.1 Timing Error Rate Tolerance for IoT Applications}, booktitle = {International Solid-State Circuits Conference}, year = {2017}, address = {San Francisco, CA, USA}, abstract = {This paper presents a 28nm SoC with a programmable FC-DNN accelerator design that demonstrates: (1) HW support to exploit data sparsity by eliding unnecessary computations (4{\texttimes} energy reduction); (2) improved algorithmic error tolerance using sign-magnitude number format for weights and datapath computation; (3) improved circuit-level timing violation tolerance in datapath logic via timeborrowing; (4) combined circuit and algorithmic resilience with Razor timing violation detection to reduce energy via VDD scaling or increase throughput via FCLK scaling; and (5) high classification accuracy (98.36\% for MNIST test set) while tolerating aggregate timing violation rates \>10-1. The accelerator achieves a minimum energy of 0.36μJ/pred at 667MHz, maximum throughput at 1.2GHz and 0.57μJ/pred, or a 10\%-margined operating point at 1GHz and 0.58μJ/pred.
\ }, keywords = {accelerators, dnn}, url = {https://doi.org/10.1109/ISSCC.2017.7870351}, author = {Paul Whatmough and Sae Lee and Hyunkwang Lee and Saketh Rama and David Brooks and Gu Wei} } @conference {whatmough201714, title = {14.3 A 28nm SoC with a 1.2 GHz 568nJ/prediction sparse deep-neural-network engine with\> 0.1 timing error rate tolerance for IoT applications}, booktitle = {2017 IEEE International Solid-State Circuits Conference (ISSCC)}, year = {2017}, pages = {242{\textendash}243}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper presents a 28nm SoC with a programmable FC-DNN accelerator design that demonstrates: (1) HW support to exploit data sparsity by eliding unnecessary computations (4{\texttimes} energy reduction); (2) improved algorithmic error tolerance using sign-magnitude number format for weights and datapath computation; (3) improved circuit-level timing violation tolerance in datapath logic via timeborrowing; (4) combined circuit and algorithmic resilience with Razor timing violation detection to reduce energy via VDD scaling or increase throughput via FCLK scaling; and (5) high classification accuracy (98.36\% for MNIST test set) while tolerating aggregate timing violation rates \>10-1. The accelerator achieves a minimum energy of 0.36μJ/pred at 667MHz, maximum throughput at 1.2GHz and 0.57μJ/pred, or a 10\%-margined operating point at 1GHz and 0.58μJ/pred.
\ }, url = {https://doi.org/10.1109/ISSCC.2017.7870351}, author = {Whatmough N and Sae Lee and Hyunkwang Lee and Saketh Rama and David Brooks and Gu Wei} } @conference {chaput201721, title = {21.5 A 3-to-5V input 100V pp output 57.7 mW 0.42\% THD+ N highly integrated piezoelectric actuator driver}, booktitle = {2017 IEEE International Solid-State Circuits Conference (ISSCC)}, year = {2017}, pages = {360{\textendash}361}, publisher = {IEEE}, organization = {IEEE}, address = {San Francisco, CA, USA}, abstract = {Piezoelectric actuators are used in a growing range of applications, e.g., haptic feedback systems, cooling fans, and microrobots. However, to fully realize their potential, these actuators require drivers able to efficiently generate high-voltage (\>100V pp ) low frequency (\<;300Hz) analog waveforms from a low-voltage source (3-to-5V) with small form factor. Certain applications, such as piezoelectric (PZT) cooling fans, further demand low distortion waveforms (THD+N \<; 1\%) to minimize sound emission from the actuator. Existing solutions for small PZT drivers typically rely on designs comprising a power converter to step up a low voltage followed by a high-voltage amplifier [1,2,3]. Although envelope tracking can help reduce amplifier power [3], none of these designs can recover the energy stored on the actuator to maximize efficiency. And while a differential bidirectional flyback converter [4] can recover energy, it requires four inductors, thereby incurring large size penalty. This paper introduces a single-inductor, highly integrated, bidirectional, high-voltage actuator driver that achieves 12.6{\texttimes} lower power and 2.1{\texttimes} lower THD+N at a similar size to the currently available state-of-the art solution [1]. Measured results from an IC prototype demonstrate 200Hz sinusoidal waveforms up to 100V pp with 0.42\% THD+N from a 3.6V source while dissipating 57.7mW to drive a 150nF capacitor. Beyond PZT actuators, the IC can also drive any type of capacitive load, e.g., electrostatic and electroactive polymer actuators.}, url = {https://doi.org/10.1109/ISSCC.2017.7870410}, author = {Simon Chaput and David Brooks and Gu Wei} } @article {adolf2017design, title = {The Design and Evolution of Deep Learning Workloads}, journal = {IEEE MICRO}, volume = {37}, year = {2017}, pages = {18{\textendash}21}, publisher = {IEEE COMPUTER SOC 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA~{\textellipsis}}, author = {Robert Adolf and Saketh Rama and Brandon Reagen and Gu Wei and David Brooks} } @booklet {wei2017soc, title = {An SoC Platform Architecture for Mini Autonomous Drones}, howpublished = {National Science Foundation Award Abstract $\#$ 1551044}, year = {2017}, publisher = {Harvard University Cambridge United States}, url = {https://nsf.gov/awardsearch/showAward?AWD_ID=1551044}, author = {Gu Wei and David Brooks} } @conference {Shao2016, title = {Co-Designing Accelerators and SoC Interfaces using gem5-Aladdin}, booktitle = {International Symposium on Microarchitecture (MICRO)}, year = {2016}, address = {Taipei, Taiwan}, abstract = {Increasing demand for power-efficient, high- performance computing has spurred a growing number and diversity of hardware accelerators in mobile and server Systems on Chip (SoCs). This paper makes the case that the co-design of the accelerator microarchitecture with the system in which it belongs is critical to balanced, efficient accelerator microarchitectures. We find that data movement and coherence management for accelerators are significant yet often unaccounted components of total accelerator runtime, resulting in misleading performance predictions and inefficient accelerator designs. To explore the design space of accelerator-system co-design, we develop gem5-Aladdin, an SoC simulator that captures dynamic interactions between accelerators and the SoC platform, and validate it to within 6\% against real hardware. Our co-design studies show that the optimal energy-delay-product (EDP) of an accelerator microarchitecture can improve by up to 7.4x when system-level effects are considered compared to optimizing accelerators in isolation.}, keywords = {accelerators, aladdin}, url = {https://ieeexplore.ieee.org/document/7783751}, author = {Yakun Shao and Sam Xi and Vijayalakshmi Srinivasan and Gu Wei and David Brooks} } @conference {Adolf2016, title = {Fathom: Reference Workloads for Modern Deep Learning Methods}, booktitle = {IEEE International Symposium on Workload Characterization}, year = {2016}, abstract = {Deep learning has been popularized by its recent successes on challenging artificial intelligence problems. One of the reasons for its dominance is also an ongoing challenge: the need for immense amounts of computational power. Hardware architects have responded by proposing a wide array of promising ideas, but to date, the majority of the work has focused on specific algorithms in somewhat narrow application domains. While their specificity does not diminish these approaches, there is a clear need for more flexible solutions. We believe the first step is to examine the characteristics of cutting edge models from across the deep learning community. Consequently, we have assembled Fathom: a collection of eight archetypal deep learning workloads for study. Each of these models comes from a seminal work in the deep learning community, ranging from the familiar deep convolutional neural network of Krizhevsky et al., to the more exotic memory networks from Facebook{\textquoteright}s AI research group. Fathom has been released online, and this paper focuses on understanding the fundamental performance characteristics of each model. We use a set of application-level modeling tools built around the TensorFlow deep learning framework in order to analyze the behavior of the Fathom workloads. We present a breakdown of where time is spent, the similarities between the performance profiles of our models, an analysis of behavior in inference and training, and the effects of parallelism on scaling.}, keywords = {dnn, machine learning}, url = {https://doi.org/10.48550/arXiv.1608.06581}, author = {Robert Adolf and Saketh Rama and Brandon Reagen and Gu Wei and David Brooks} } @article {Tong2016, title = {A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications}, journal = {IEEE Journal of Solid-State Circuits}, volume = {51}, year = {2016}, pages = {2142{\textendash}2152}, abstract = {This work presents a fully integrated 4-to-1 DC-DC symmetric ladder switched-capacitor converter (SLSCC) for voltage stacking applications. The SLSCC absorbs inter-layer load power mismatch to provide minimum voltage guarantees for the internal rails of a multicore system that implements four-way voltage stacking. A new hybrid feedback control scheme reduces the voltage ripple across stacked voltage layers for high levels of current mismatch, a condition that exacerbates voltage noise in conventional SC converters. Furthermore, the proposed SLSCC dynamically allocates valuable flying capacitor resources according to different load conditions, which improves conversion efficiency and supports more power mismatch between the layers. Implemented in TSMC{\textquoteright}s 40G process, the SLSCC converts a 3.6 V input voltage down to four stacked output voltage layers, each nominally at 900 mV.}, keywords = {voltage-regulator, voltage-stacking}, url = {https://doi.org/10.1109/JSSC.2016.2580598}, author = {Tao Tong and Sae Lee and Xuan Zhang and David Brooks and Gu Wei} } @conference {Reagen2016, title = {Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators}, booktitle = {International Symposium on Computer Architecture (ISCA)}, year = {2016}, address = {Seoul, Korea (South)}, abstract = {The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous datatype optimization reduces power by 1.5{\texttimes}; aggressive, inline predication and pruning of small activity values further reduces power by 2.0{\texttimes}; and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7{\texttimes} through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1{\texttimes} power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.}, keywords = {accelerators, dnn, machine learning, power}, url = {https://doi.org/10.1109/ISCA.2016.32}, author = {Brandon Reagen and Paul Whatmough and Robert Adolf and Saketh Rama and Hyunkwang Lee and Sae Kyu Lee and Jos{\'e} Hern{\'a}ndez-Lobato and Gu Wei and David Brooks} } @article {jafferis2016multilayer, title = {Multilayer laminated piezoelectric bending actuators: design and manufacturing for optimum power density and efficiency}, journal = {Smart Materials and Structures}, volume = {25}, year = {2016}, pages = {055033}, publisher = {IOP Publishing}, abstract = {

In previous work we presented design and manufacturing rules for optimizing the energy density of piezoelectric bimorph actuators through the use of laser-induced melting, insulating edge coating, and features for rigid ground attachments to maximize force output, as well as a pre-stacked technique to enable mass customization. Here we adapt these techniques to bending actuators with four active layers, which utilize thinner material layers. This allows the use of lower operating voltages, which is important for overall power usage optimization, as typical small-scale power supplies are low-voltage and the efficiency of boost-converter and drive circuitry increases with decreasing output voltage. We show that this optimization results in a 24\%{\textendash}47\% reduction in the weight of the required power supply (depending on the type of drive circuit used). We also present scaling arguments to determine when multi-layer actuator are preferable to thinner actuators, and show that our techniques are capable of scaling down to sub-mg weight actuators.

}, url = {http://dx.doi.org/10.1088/0964-1726/25/5/055033}, author = {Jafferis T and Mario Lok and Winey Nastasia and Gu Wei and Wood J} } @booklet {karpelson2016system, title = {System and method for efficient drive of capacitive actuators with voltage amplification}, year = {2016}, note = {US Patent 9,257,936}, abstract = {A circuit for driving a plurality of capacitive actuators, the circuit having a low-voltage side, a high voltage side and a flyback transformer between the two. The low-voltage side comprises first and second pairs of low-side switches connected in series across an input voltage. The flyback transformer has a primary winding connected to the two pairs of switches. The high-voltage side has a pair of switches connected between the secondary winding of the flyback transformer and a ground and a plurality of capacitive loads and bidirectional switches to connect the loads to the secondary winding of the flyback transformer and a ground.}, author = {Karpelson, Michael and Wood J and Gu Wei} } @conference {hernandez2016designing, title = {Designing neural network hardware accelerators with decoupled objective evaluations}, booktitle = {NIPS workshop on Bayesian Optimization}, year = {2016}, pages = {10}, abstract = {Software-based implementations of deep neural network predictions consume large amounts of energy, limiting their deployment in power-constrained environments. Hardware acceleration is a promising alternative. However, it is challenging to efficiently design accelerators that have both low prediction error and low energy consumption. Bayesian optimization can be used to accelerate the design problem. However, most of the existing techniques collect data in a coupled way by always evaluating the two objectives (energy and error) jointly at the same input, which is inefficient. Instead, in this work we consider a decoupled approach in which, at each iteration, we choose which objective to evaluate next and at which input. We show that considering decoupled evaluations produces better solutions when computational resources are limited. Our results also indicate that evaluating the prediction error is more important than evaluating the energy consumption.}, url = {https://jmhldotorg.files.wordpress.com/2013/10/hardwarenn_nipsworkshopbo20161.pdf}, author = {Jos{\'e} Lobato and Gelbart, Michael A and Brandon Reagen and Robert Adolf and Hern{\'a}ndez-Lobato, Daniel and Whatmough, Paul N and David Brooks and Gu-Yeon Wei and Adams, Ryan P} } @booklet {wei2016methods, title = {Methods and apparatus for parallel processing}, year = {2016}, note = {US Patent App. 14/898,894}, author = {Gu Wei and David Brooks and Simone Campanoni and Kevin Brownell and Svilen Kanev} } @conference {Reagen_MSBARC_2015, title = {The MachSuite Benchmark}, booktitle = {Boston Area Architecture Workshop (BARC)}, year = {2015}, address = {Raleigh, NC, USA}, abstract = {Recent high-level synthesis and accelerator-related architecture papers show a great disparity in workload selection. To improve standardization within the accelerator research community, we present MachSuite, a collection of 19 benchmarks for evaluating high-level synthesis tools and accelerator-centric architectures. MachSuite spans a broad application space, captures a variety of different program behaviors, and provides implementations tailored towards the needs of accelerator designers and researchers, including support for high-level synthesis. We illustrate these aspects by characterizing each benchmark along five different dimensions, highlighting trends and salient features.}, keywords = {accelerators, machsuite}, url = {https://ieeexplore.ieee.org/document/6983050}, author = {Brandon Reagen and Robert Adolf and Gu Wei and David Brooks} } @conference {Lok2015, title = {A Power Electronics Unit to Drive Piezoelectric Actuators for Flying Microrobots}, booktitle = {IEEE Custom Integrated Circuits Conference (CICC)}, year = {2015}, abstract = {This paper describes a power electronics unit (PEU) for an insect-scale flapping-wing robot. Three power saving techniques used in the actuator driver of the PEU {\textemdash} envelope tracking, dynamic common mode, and charge sharing {\textemdash} reduce power consumption while retaining weight benefits of an inductor-less linear driver. A pair of actuator driver ICs energize four 15nF capacitor loads, which represent the piezoelectric actuators of a flapping-wing robot. The PEU consumes 290mW, which translates to 37\% lower power compared to a design without these power saving techniques.}, keywords = {robobees}, url = {https://micro.seas.harvard.edu/papers/Lok_CICC_2015.pdf}, author = {Mario Lok and Xuan Zhang and Elizabeth Helblinh and Robert Wood and David Brooks and Gu Wei} } @article {chung20157, title = {A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS}, journal = {Analog Integrated Circuits and Signal Processing}, volume = {85}, year = {2015}, pages = {299{\textendash}310}, publisher = {Springer US}, abstract = {This paper presents a 7.5 GS/s, 4.5 bit flash analog-to-digital converter (ADC) for high-speed backplane communication. A two-stage track-and-hold (T/H) structure enables high input bandwidth and low power consumption at the same time. A sampling clock duty cycle control technique, which allocates more tracking time to the bandwidth-limited second T/H stage, facilitates high sampling rates. A digital offset correction scheme compensates both random and systematic offsets due to process variation and T/H amplifier gain nonlinearity, simultaneously. Two test-chip prototypes were fabricated in a 65 nm CMOS process. Experimental results of a standalone ADC chip demonstrate 3.8 effective number of bits (ENOB) at 7.5 GS/s. The figure-of-merit (FOM) of the standalone ADC is 0.49 pJ/conversion-step. The second test chip combines two ADCs together in order to demonstrate a time-interleaved ADC (TI-ADC) for use in high-speed backplane receivers. The TI-ADC operates at 10.24 GS/s while achieving 3.5 ENOB and 0.65 pJ/conversion-step FOM.}, url = {http://dx.doi.org/10.1007/s10470-015-0624-x}, author = {Chung, Hayun and Deniz, Toprak and Rylyakov, Alexander and Bulzacchelli, John and Friedman, Daniel and Gu Wei} } @conference {Whatmough2015, title = {A 0.6V All-Digital Body-Coupled Wakeup Transceiver for IoT Applications}, booktitle = {IEEE Symposium on VLSI Circuits (VLSIC)}, year = {2015}, address = {Kyoto, Japan}, abstract = {A body-coupled symmetric wakeup transceiver is proposed for always-on device discovery in IoT applications requiring security and low-power consumption. The wakeup transceiver (WTRx) is implemented in 65nm CMOS, using digital logic cells and operates at 0.6V. A directly-modulated open-loop DCO generates an OOK-modulated 10MHz carrier, with a frequency-locked loop for intermittent calibration. A passive receiver incorporates a digital IO cell as hysteretic comparator, with a two-phase correlator bank. A novel MAC scheme allows for duty-cycling in both transmitter and receiver. Measured power consumption is 3.54μW, with sensitivity of 88mV and maximum wakeup latency of 150ms.}, keywords = {iot}, url = {https://doi.org/10.1109/VLSIC.2015.7231338}, author = {Paul Whatmough and George Smart and Shidhartha Das and Yiannis Andreopoulos and David Bull} } @conference {Zhang2015, title = {A Multi-Chip System Optimized for Insect-Scale Flapping-Wing Robots}, booktitle = {IEEE Symposium on VLSI Circuits (VLSIC)}, year = {2015}, abstract = {We demonstrate a battery-powered multi-chip system optimized for insect-scale flapping wing robots that meets the tight weight limit and real-time performance demands of autonomous flight. Measured results show open-loop wing flapping driven by a power electronics unit and energy efficiency improvements via hardware acceleration.}, keywords = {accelerators, robobees}, url = {https://doi.org/10.1109/VLSIC.2015.7231246}, author = {Xuan Zhang and Mario Lok and Tao Tong and Simon Chaput and Sae Lee and Brandon Reagen and Hyunkwang Lee and David Brooks and Gu Wei} } @proceedings {reagenpdf, title = {From PDF to GDS: Designing the RoboBee SoC}, year = {2015}, abstract = {Developing the Robobee was a multi-discipline, 5-year project funded by a National Science Foundation Expeditions in Computing award with the goal of achieving autonomous flight with a bee-sized micro-robot [2]. The intent of the research was to help re-stabilize the declining bee population which researchers have shown could have devastating effects on the earths ecosystem. Bees are remarkably efficient; their skeleton weighs almost nothing: requiring minimal lift to takeoff and sustain flight; their brains are small: pre-programmed with a minimal set of instincts necessary for the colonies survival. Their capabilities under such stringent weight and compute limitations makes them a prime target for pushing what modern robotics and computer systems can do. The weight and power limits require a custom System-onChip (SoC) be built. Conventional off-chip voltage regulators are heavy and bulky, and thus cannot fit under the weight and form factor of the robotic bee. Commercial Off-The-Shelf parts (COTS) micro-controllers consume too much power to perform the required computation for autonomous flight. The solution is to pack as much IP onto a single die. SoCs have been the trend of all semi-conductor companies over the past decade from mobile and embedded to server grade solutions. In this paper we recount our experiences designing such a chip. We highlight the major challenges faced when designing for such a unique form factor, how designs and specifications were set by each collaborating lab, the difficulties of integrating a plethora of IP consisting of in-house digital and analog blocks, and the design flows we used. We also discuss how invaluable HLS was in reducing the engineering burden, focusing design efforts at higher levels of abstraction, and an overall successful tape-out.}, url = {https://www.csl.cornell.edu/warp2015/abstracts/reagen-robobee-warp2015.pdf}, author = {Brandon Reagen and Zhang, Xaun and David Brooks and Gu Wei} } @conference {kanev15wsc, title = {Profiling a Warehouse-Scale Computer}, booktitle = {International Symposium on Computer Architecture (ISCA)}, year = {2015}, abstract = {With the increasing prevalence of warehouse-scale (WSC) and cloud computing, understanding the interactions of server applications with the underlying microarchitecture becomes ever more important in order to extract maximum performance out of server hardware. To aid such understanding, this paper presents a detailed microarchitectural analysis of live datacenter jobs, measured on more than 20,000 Google machines over a three year period, and comprising thousands of different applications. We first find that WSC workloads are extremely diverse, breeding the need for architectures that can tolerate application variability without performance loss. However, some patterns emerge, offering opportunities for co-optimization of hardware and software. For example, we identify common building blocks in the lower levels of the software stack. This \"datacenter tax\" can comprise nearly 30\% of cycles across jobs running in the fleet, which makes its constituents prime candidates for hardware specialization in future server systems-on-chips. We also uncover opportunities for classic microarchitectural optimizations for server processors, especially in the cache hierarchy. Typical workloads place significant stress on instruction caches and prefer memory latency over bandwidth. They also stall cores often, but compute heavily in bursts. These observations motivate several interesting directions for future warehouse-scale computers.}, keywords = {datacenter}, url = {https://doi.org/10.1145/2749469.2750392}, author = {Svilen Kanev and Juan Darago and Kim Hazelwood and Moseley, Tipp and Gu Wei and David Brooks} } @conference {Lee2015, title = {A 16-Core Voltage-Stacked System with an Integrated Switched-Capacitor DC-DC Converter}, booktitle = {IEEE Symposium on VLSI Circuits (VLSIC)}, volume = {99}, year = {2015}, pages = {1-14}, address = {Kyoto, Japan}, abstract = {A 16-core voltage-stacked IC integrated with a switched-capacitor DC-DC converter demonstrates efficient power delivery. To overcome inter-layer voltage noise issues, the test chip implements and evaluates the benefits of self-timed clocking and clock-phase interleaving. The integrated converter offers minimum voltage guarantees and further reduces voltage noise.}, keywords = {voltage-regulator, voltage-stacking}, url = {https://doi.org/10.1109/VLSIC.2015.7231306}, author = {Sae Lee and Tao Tong and Xuang Zhang and David Brooks and Gu Wei} } @article {shao2015aladdin, title = {The aladdin approach to accelerator design and modeling}, journal = {IEEE Micro}, volume = {35}, year = {2015}, pages = {58{\textendash}70}, publisher = {IEEE}, abstract = {Hardware specialization, in the form of datapath and control circuitry customized to particular algorithms or applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerators relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but also are slow and tedious to use, making large design space exploration infeasible. To overcome this problem, the authors developed Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrated its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9, 4.9, and 6.6 percent with respect to RTL implementations. Integrated with architecture-level general-purpose core and memory hierarchy simulators, Aladdin provides researchers with a fast but accurate way to model the power and performance of accelerators in an SoC environment.}, url = {https://doi.org/10.1109/MM.2015.50}, author = {Yakun Shao and Brandon Reagen and Gu Wei and David Brooks} } @conference {Campanoni2015_cgo, title = {HELIX-UP: Relaxing Program Semantics to Unleash Parallelization}, booktitle = {International Symposium on Code Generation and Optimization (CGO)}, year = {2015}, pages = {235{\textendash}245}, address = {San Francisco, CA, USA}, abstract = {Automatic generation of parallel code for general-purpose commodity processors is a challenging computational problem. Nevertheless, there is a lot of latent thread-level parallelism in the way sequential programs are actually used. To convert latent parallelism into performance gains, users may be willing to compromise on the quality of a program{\'s} results. We have developed a parallelizing compiler and runtime that substantially improve scalability by allowing parallelized code to briefly sidestep strict adherence to language semantics at run time. In addition to boosting performance, our approach limits the sensitivity of parallelized code to the parameters of target CPUs (such as core-to-core communication latency) and the accuracy of data dependence analysis.}, keywords = {helix, up}, url = {http://www.eecs.harvard.edu/~xan/lib/exe/fetch.php?media=research:cgo2015_paper.pdf}, author = {Simone Campanoni and Glenn Holloway and Gu Wei and David Brooks} } @conference {Xi2015_hpca, title = {Quantifying Sources of Error in McPAT and Potential Impacts on Architectural Studies}, booktitle = {International Symposium on High Performance Computer Architecture (HPCA)}, year = {2015}, abstract = {Architectural power modeling tools are widely used by the computer architecture community for rapid evaluations of high-level design choices and design space explorations. Currently, McPAT is the de facto power model, but the literature does not yet contain a careful examination of its modeling accuracy. In addition, the issue of how greatly power modeling error can affect architectural-level studies has not been quantified before. In this work, we present the first rigorous assessment of McPAT{\textquoteright}s core power and area models with a detailed, validated power modeling toolchain used in current industrial practice. We find that McPAT{\textquoteright}s predictions can have significant error because some of the models are either incomplete, too high-level, or assume implementations of structures that differ from that of the core at hand. We demonstrate that large errors are possible when using McPAT{\textquoteright}s dynamic power estimates in the context of voltage noise and thermal hotspots, but for steady-state properties, accurately modeling leakage power is more important. Based on our analysis, we are able to provide guidelines for creating accurate McPAT models, even without access to detailed industrial power modeling tools. We conclude that in spite of its accuracy gaps, McPAT is still a very useful tool for many architectural studies, and its limitations can often be adequately addressed for a given research study of interest.}, keywords = {mcpat}, url = {http://www.samxi.org/papers/xi_hpca2015.pdf}, author = {Sam Xi and Hans Jacobson and Pradip Bose and Gu Wei and David Brooks} } @booklet {reddi2015adaptive, title = {Adaptive event-guided system and method for avoiding voltage emergencies}, year = {2015}, note = {US Patent 8,949,666}, abstract = {In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.}, author = {Vijay Reddi and Meeta Gupta and Glenn Holloway and Gu Wei and Michael Smith and David Brooks} } @conference {Reagen_ACC_BARC_2015, title = {How Hardware Accelerators Trade-Off Pipelining and Parallelism to Maximize Efficiency}, booktitle = {Boston Area Architecture Workshop (BARC)}, year = {2015}, keywords = {accelerators}, url = {http://www.eecs.harvard.edu/~reagen/papers/AccModel.pdf}, author = {Brandon Reagen and Gu Wei and David Brooks} } @conference {Shao2015_scaw, title = {Toward Cache-Friendly Hardware Accelerators}, booktitle = {HPCA Sensors and Cloud Architectures Workshop (SCAW)}, year = {2015}, abstract = {Increasing demand for power-efficient, high-performance computing has spurred a growing number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as servers and desktops. Despite their energy efficiency, fixed-function accelerators lack programmability, especially compared with general-purpose processors. Today{\textquoteright}s accelerators rely on software-managed scratchpad memory and Direct Memory Access (DMA) to provide fixed-latency memory access and data transfer, which leads to significant chip resource and software engineering costs. On the other hand, hardware-managed caches with support for virtual memory and cache coherence are well-known to ease programmability in general-purpose processors, but these features are not commonly supported in today{\textquoteright}s fixed-function accelerators. As a first step toward cache-friendly accelerator design, this paper discusses limitations of scratchpad-based memories in today{\textquoteright}s accelerators, identifies challenges to support hardware-managed caches, and explores opportunities to ease the cache integration.}, keywords = {accelerators, aladdin}, url = {http://www.eecs.harvard.edu/~shao/papers/shao2015-scaw.pdf}, author = {Yakun Shao and Sam Xi and Viji Srinivasan and Gu Wei and David Brooks} } @conference {al2015unified, title = {Unified Cache: A Case for Low-Latency Communication}, booktitle = {3rd International Workshop on Parallelism in Mobile Platforms (PRISM). Portland, OR, USA}, year = {2015}, abstract = {Increasing computational demand on mobile devices calls for energy-friendly solutions for accelerating single programs. In the multicore era, thread level parallelism (TLP) can accelerate single-threaded programs without requiring power-hungry cores. HELIX-RC, a recently proposed co-design between the HELIX parallelizing compiler and its target architecture, shows that substantial TLP can be extracted from loops with small bodies by optimizing core-to-core communication. Previously, the effectiveness of the HELIX-RC approach has been demonstrated through simulation. In this paper, we evaluate a HELIXRC-like solution on a real platform. We have developed a simplified version of the HELIX-RC architecture that we call unified cache, and we have implemented it on an FPGA board. Our design augments a multicore platform with a simplified ring cache{\textemdash}the architectural component of the HELIX-RC co-design. With the aid of microbenchmarks, our FPGA prototype confirms the HELIX-RC findings. David Brooks After describing both the ring cache and the parallel code generated by the HELIX compiler, we sketch the design of the unified cache and we evaluate its implementation on a Xilinx VC707 FPGA board.}, author = {Al-Hawaj, Khalid and Simone Campanoni and Gu Wei and David Brooks} } @conference {Reagen2014, title = {MachSuite: Benchmarks for Accelerator Design and Customized Architectures}, booktitle = {IEEE International Symposium on Workload Characterization (IISWC)}, year = {2014}, abstract = {Recent high-level synthesis and accelerator-related architecture papers show a great disparity in workload selection among projects and research groups. To provide standardization within the accelerator research community, we present MachSuite, a benchmark suite for high-level synthesis tools and accelerator-centric architectures. MachSuite is the compilation of carefully selected workloads to cover a diverse application space and algorithm choices. All the benchmarks in MachSuite are implemented to be well suited for high-level synthesis. A thorough characterization further demonstrates the diverse behaviors among benchmarks, representative of different customization challenges. MachSuite enables commensurability across research projects while mitigating the burden of accelerator implementation and workload selection.}, keywords = {accelerators}, url = {10.1109/IISWC.2014.6983050}, author = {Brandon Reagen and Robert Adolf and Sophia Shao and Gu Wei and David Brooks} } @conference {kanev2014tradeoffs, title = {Tradeoffs between power management and tail latency in warehouse-scale applications}, booktitle = {2014 IEEE International Symposium on Workload Characterization (IISWC)}, year = {2014}, pages = {31{\textendash}40}, publisher = {IEEE}, organization = {IEEE}, abstract = {The growth in datacenter computing has increased the importance of energy-efficiency in servers. Techniques to reduce power have brought server designs close to achieving energy-proportional computing. However, they stress the inherent tradeoff between aggressive power management and quality of service (QoS) - the dominant metric of performance in datacenters. In this paper, we characterize this tradeoff for 15 benchmarks representing workloads from Google{\textquoteright}s datacenters. We show that 9 of these benchmarks often toggle their cores between short bursts of activity and sleep. In doing so, they stress sleep selection algorithms and can cause tail latency degradation or missed potential for power savings of up to 10\% on important workloads like web search. However, improving sleep selection alone is not sufficient for large efficiency gains on current server hardware. To guide the direction needed for such large gains, we profile datacenter applications for susceptibility to dynamic voltage and frequency scaling (DVFS). We find the largest potential in DVFS which is cognizant of latency/power tradeoffs on a workload-per-workload basis.}, url = {https://doi.org/10.1109/IISWC.2014.6983037}, author = {Svilen Kanev and Kim Hazelwood and Gu Wei and David Brooks} } @conference {kanev14epb, title = {Tradeoffs between Power Management and Tail Latency in Warehouse-Scale Applications}, booktitle = {International Symposium on Workload Characterization (IISWC)}, year = {2014}, pages = {31-40}, publisher = {IEEE}, organization = {IEEE}, abstract = {The growth in datacenter computing has increased the importance of energy-efficiency in servers. Techniques to reduce power have brought server designs close to achieving energy-proportional computing. However, they stress the inherent tradeoff between aggressive power management and quality of service (QoS) {\textendash} the dominant metric of performance in datacenters. In this paper, we characterize this tradeoff for 15 benchmarks representing workloads from Google{\textquoteright}s datacenters. We show that 9 of these benchmarks often toggle their cores between short bursts of activity and sleep. In doing so, they stress sleep selection algorithms and can cause tail latency degradation or missed potential for power savings of up to 10\% on important workloads like web search. However, improving sleep selection alone is not sufficient for large efficiency gains on current server hardware. To guide the direction needed for such large gains, we profile datacenter applications for susceptibility to dynamic voltage and frequency scaling (DVFS). We find the largest potential in DVFS which is cognizant of latency/power tradeoffs on a workload-per-workload basis.}, keywords = {datacenter}, url = {https://doi.ieeecomputersociety.org/10.1109/IISWC.2014.6983037}, author = {Svilen Kanev and Kim Hazelwood and Gu Wei and David Brooks} } @conference {lyons2014multi, title = {Multi-accelerator system development with the shrinkfit acceleration framework}, booktitle = {2014 IEEE 32nd International Conference on Computer Design (ICCD)}, year = {2014}, pages = {75{\textendash}82}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper introduces the ShrinkFit accelerator framework, which simplifies the design of systems combining multiple accelerators. A single ShrinkFit system design can be deployed to FPGAs large and small, without time-consuming architectural parameter surveys. We describe four ShrinkFit accelerators implemented for an FPGA-based robotic bee brain prototype and demonstrate the flexibility of ShrinkFit with low performance overheads (under 10\% on average) and low resource overheads (0-8\% for accelerators and under 2\% for hard logic blocks).}, url = {https://doi.org/10.1109/ICCD.2014.6974665}, author = {Michael Lyons and Gu Wei and David Brooks} } @conference {Lyons2014, title = {Multi-accelerator system development with the ShrinkFit acceleration framework}, booktitle = {International Conference on Computer Design}, year = {2014}, address = {Seoul, Korea (South)}, abstract = {This paper introduces the ShrinkFit accelerator framework, which simplifies the design of systems combining multiple accelerators. A single ShrinkFit system design can be deployed to FPGAs large and small, without time-consuming architectural parameter surveys. We describe four ShrinkFit accelerators implemented for an FPGA-based robotic bee brain prototype and demonstrate the flexibility of ShrinkFit with low performance overheads (under 10\% on average) and low resource overheads (0-8\% for accelerators and under 2\% for hard logic blocks).}, keywords = {accelerator-store, accelerators}, url = {https://doi.org/10.1109/ICCD.2014.6974665}, author = {Michael Lyons and Gu Wei and David Brooks} } @conference {shao2013isca, title = {Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures}, booktitle = {International Symposium on Computer Architecture (ISCA)}, year = {2014}, abstract = {Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9\%, 4.9\%, and 6.6\% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.}, keywords = {aladdin}, url = {https://doi.org/10.1109/ISCA.2014.6853196}, author = {Yakun Shao and Brandon Reagen and Gu Wei and David Brooks} } @conference {campanoni2014isca, title = {HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs}, booktitle = {International Symposium on Computer Architecture (ISCA)}, volume = {42}, year = {2014}, pages = {217{\textendash}228}, edition = {3}, abstract = {Data dependences in sequential programs limit paralleliza- tion because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85{\texttimes} performance speedup for six SPEC CINT2000 benchmarks.}, keywords = {helix}, url = {https://doi.org/10.1145/2678373.2665705}, author = {Simone Campanoni and Kevin Brownell and Svilen Kanev and Timothy Jones and Gu Wei and David Brooks} } @patent {lin2014voltage, title = {Voltage regulator integrated with semiconductor chip}, volume = {US8749021B2}, year = {2014}, note = {US Patent 8,749,021}, edition = {United States of America}, chapter = {US}, abstract = {The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.}, url = {https://patents.google.com/patent/US8749021}, author = {Lin Shiung and Gu Wei} } @booklet {bose2014cross, title = {Cross-Layer Modeling Framework for Energy-Efficient Resilience}, year = {2014}, publisher = {IBM TJ Watson Research Center Yorktown Heights United States}, abstract = {

We describe a novel cross-layer, resilience focused integrated modeling framework. This is targeted to help define ultra energy-efficient embedded systems in the post-14nm CMOS design era, without compromising system-level resilience. The targeted application domain is represented by the suite of applications and kernels announced as part of the ongoing PERFECT program sponsored by DARPA MTO.

}, url = {https://apps.dtic.mil/sti/citations/AD1026057}, author = {Pradip Bose and David Brooks and Mitra, Subhasish and Rajamani, Karthick and Stan, Mircea and Kevin Skadron and Gu Wei} } @conference {Zhang2014, title = {Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip}, booktitle = {IEEE Transactions on Circuits and Systems (TCAS)}, volume = {PP}, year = {2014}, abstract = {A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme that can tolerate supply noise and improve performance when implemented with an integrated voltage regulator (IVR). Measurements from a {\textquoteleft}brain{\textquoteright} SoC, implemented in 40 nm CMOS, demonstrate 2 {\texttimes} performance improvement with adaptive-frequency clocking over conventional fixed-frequency clocking. Combining adaptive-frequency clocking with open-loop IVR extends error-free operation to a wider battery voltage range (2.8 to 3.8 V) with higher average performance.}, keywords = {robobees}, url = {https://doi.org/10.1109/TCSI.2014.2312490}, author = {Xuan Zhang and Tao Tong and David Brooks and Gu Wei} } @conference {campanoni2014xml, title = {Breaking Cyclic-Multithreading Parallelization with XML Parsing}, booktitle = {International Workshop on Parallelism in Mobile Platforms (PRISM)}, year = {2014}, abstract = {HELIX-RC, a modern re-evaluation of the cyclic-multithreading (CMT) compiler technique, extracts threads from sequential code automatically. As a CMT approach, HELIX-RC gains performance by running iterations of the same loop on different cores in a multicore. It successfully boosts performance for several SPEC CINT benchmarks previously considered unparallelizable. However, this paper shows there are workloads with different characteristics, which even idealized CMT cannot parallelize. We identify how to overcome an inherent limitation of CMT for these workloads. CMT techniques only run iterations of a single loop in parallel at any given time. We propose exploiting parallelism not only within a single loop, but also among multiple loops. We call this execution model Multiple CMT (MCMT), and show that it is crucial for auto-parallelizing a broader class of workloads. To highlight the need for MCMT, we target a workload that is naturally hard for CMT {\textendash} parsing XML-structured data. We show that even idealized CMT fails on XML parsing. Instead, MCMT extracts speedups up to 3.9x on 4 cores.}, keywords = {helix}, url = {http://www.eecs.harvard.edu/~skanev/papers/prism14xml.pdf}, author = {Simone Campanoni and Svilen Kanev and Kevin Brownell and Gu Wei and David Brooks} } @conference {Zhang2013b, title = {A 20uW 10MHz Relaxation Oscillator with Adaptive Bias and Fast Self-Calibration in 40nm CMOS for Micro-Aerial Robotics Application}, booktitle = {IEEE Asian Solid-State Circuits Conference (ASSCC)}, year = {2013}, abstract = {Efficient actuation control of flapping-wing microrobots requires a low-power frequency reference with good absolute accuracy. To meet this requirement, we designed a fully-integrated 10MHz relaxation oscillator in a 40nm CMOS process. By adaptively biasing the continuous-time comparator, we are able to achieve a power consumption of 20μW, a 68\% reduction to the conventional fixed bias design. A built-in self-calibration controller enables fast post-fabrication calibration of the clock frequency. Measurements show a frequency drift of 1.2\% as the battery voltage changes from 3V to 4.1V.}, keywords = {robobees}, url = {10.1109/ASSCC.2013.6691075}, author = {Xuan Zhang and David Brooks and Gu Wei} } @conference {Tong2013, title = {A Fully Integrated Battery-Connected Switched-Capacitor 4:1 Voltage Regulator with 70\% Peak Efficiency Using Bottom-Plate Charge Recycling}, booktitle = {IEEE Custom Integrated Circuits Conference (CICC)}, year = {2013}, abstract = {This work presents a switched-capacitor (SC) DC-DC voltage regulator that converts a 3.7V battery voltage down to ~0.8V in order to power the {\textquoteleft}brain{\textquoteright} SoC of a flapping-wing microrobotic bee. A cascade of two 2:1 SC converters offers high efficiency for a 4:1 conversion ratio. A charge recycling technique reduces the flying capacitor{\textquoteright}s bottom-plate parasitic loss by 50\% and overall conversion efficiency reaches 70\%. The output droop is less than 10\% of the nominal output voltage for a worst-case 47mA load step.}, keywords = {robobees}, url = {https://doi.org/10.1109/CICC.2013.6658485}, author = {Tao Tong and Xuan Zhang and Wonyoung Kim and David Brooks and Gu Wei} } @conference {Zhang2013, title = {Supply-Noise Resilient Adaptive Clocking for Battery-Powered Aerial Microrobotic System-on-Chip in 40nm CMOS}, booktitle = {IEEE Custom Integrated Circuits Conference (CICC)}, year = {2013}, abstract = {A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully-integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme that can tolerate supply noise and improve performance when implemented with an integrated voltage regulator (IVR). Measurements from a {\textquoteleft}brain{\textquoteright} SoC, implemented in 40nm CMOS, demonstrate 2{\texttimes} performance improvement with adaptive-frequency clocking over conventional fixed-frequency clocking. Combining adaptive-frequency clocking with open-loop IVR extends error-free operation to a wider battery voltage range (2.8 to 3.8V) with higher average performance.}, keywords = {robobees}, url = {https://doi.org/10.1109/CICC.2013.6658436}, author = {Xuan Zhang and Tao Tong and David Brooks and Gu Wei} } @conference {Lok2013, title = {Design and analysis of an integrated driver for piezoelectric actuators}, booktitle = {IEEE Energy Conversion Congress and Exposition}, year = {2013}, abstract = {Small-scale, highly maneuverable, flapping-wing robotic insects have a wide range of applications, including exploration, environmental monitoring, search and rescue, and surveillance. For these small-scale robots, a piezoelectric cantilever actuator driven by a high voltage drive signal is a preferred actuation mechanism. The generation of this drive signal via light and efficient power electronics is critical given the limited weight budget for the flapping-wing robot. Previous work demonstrated actuator drive circuitry using discrete power transistors and passive elements. This paper presents a new design that integrates all the power FETs into a single monolithic IC, reducing the weight of the power electronics to fit within the weight budget. This design adds the capability of driving multiple outputs to accommodate recent electromechanical design advances for flying robots.}, keywords = {robobees}, url = {https://doi.org/10.1109/ECCE.2013.6647048}, author = {Mario Lok and David Brooks and Robert Wood and Gu Wei} } @conference {zhangcharacterizing, title = {Characterizing and Evaluating Voltage Noise in Multi-Core Near-Threshold Processors}, booktitle = {International Symposium on Low Power Electronics and Design (ISLPED)}, year = {2013}, abstract = {Lowering the supply voltage to improve energy efficiency leads to higher load current and elevated supply sensitivity. In this paper, we provide the first quantitative analysis of voltage noise in multi-core near-threshold processors in a future 10nm technology across SPEC CPU2006 benchmarks. Our results reveal larger guardband requirement and significant energy efficiency loss due to power delivery nonidealities at near threshold, and highlight the importance of accurate voltage noise characterization for design exploration of energy-centric computing systems using near-threshold cores.}, url = {https://doi.org/10.1109/ISLPED.2013.6629271}, author = {Xuan Zhang and Tao Tong and Svilen Kanev and Sae Lee and Gu Wei and David Brooks} } @conference {shao2013islped, title = {Energy Characterization and Instruction-Level Energy Model of Intel{\textquoteright}s Xeon Phi Processor}, booktitle = {International Symposium on Low Power Electronics and Design (ISLPED)}, year = {2013}, abstract = {Intel{\textquoteright}s Xeon Phi is the first commercial many-core/multi-thread x86-based processor. Xeon Phi belongs to a new breed of high performance computing processors that seek high compute density as well as energy efficiency. However, no high- level energy model is available for Xeon Phi software developers to quickly evaluate and optimize energy efficiency. This work demonstrates an instruction-level energy model for the Xeon Phi processor to facilitate the development of energy-efficient software. In order to construct this model, we first characterize the energy consumption of the processor, identifying how energy per instruction scales with the number of cores, the number of active threads per core, and instruction types. Based on the energy characterization, we construct an instruction-level energy model and validate the accuracy of the model between 1\% and 5\% for real world benchmarks. We show that the energy model can be used to identify software inefficiencies for these benchmarks and find that Linpack code can be optimized to increase energy efficiency by as much as 10\%.}, keywords = {wiica}, url = {https://doi.org/10.1109/ISLPED.2013.6629328}, author = {Yakun Shao and David Brooks} } @conference {reagen2013islped, title = {Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware}, booktitle = {International Symposium on Low Power Electronics and Design (ISLPED)}, year = {2013}, abstract = {As the traditional performance gains of technology scaling diminish, one of the most promising directions is building special purpose fixed function hardware blocks, commonly referred to as accelerators. Accelerators have become prevalent in industrial SoC designs for their low power, high performance potential. In this work we explore thousands of implementations of classical software workloads in hardware. This thorough, detailed design space search of hardware accelerators gives architects a quantita- tive way to reason about the differences in implementations. The exploration presented in this work shows that the space is full of poor design choices. By thoroughly analyzing each benchmark, we show which provide the most performance when implemented in hardware given a fixed power budget and explain which design techniques work best for each workload.}, keywords = {aladdin}, url = {https://doi.org/10.1109/ISLPED.2013.6629329}, author = {Brandon Reagen and Yakun Shao and Gu Wei and David Brooks} } @article {chung2013adc, title = {ADC-based backplane receiver design-space exploration}, journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, volume = {22}, year = {2013}, pages = {1539{\textendash}1547}, publisher = {IEEE}, abstract = {Demand for higher throughput backplane communications, coupled with a desire for design portability and flexibility, has led to high-speed backplane receivers that use front-end analog-to-digital converters (ADCs) and digital equalization. Unfortunately, power and complexity of such receivers can be high and require careful design. This paper presents a parameterized ADC-based backplane receiver model that facilitates design-space exploration to optimize the tradeoffs between power and performance-an accurate behavioral model of front-end ADCs is presented for performance estimation and detailed power models for the digital equalizer (EQ) blocks are developed for power estimation. Model-based simulations suggest that comparator offset correction resolution is the most critical ADC design parameter when an overall receiver performance is concerned. Further receiver design-space exploration reveals that a Pareto optimal frontier exists, which can be used as a guideline to set the initial receiver configurations depending on a given power and performance constraints.}, url = {https://doi.org/10.1109/TVLSI.2013.2275742}, author = {Chung, Hayun and Gu Wei} } @conference {shao2013ispass, title = {ISA-Independent Workload Characterization and its Implications for Specialized Architectures}, booktitle = {International Symposium on Performance Analysis of Systems and Software (ISPASS)}, year = {2013}, publisher = { }, organization = { }, abstract = {Specialized architectures will become increasingly important as the computing industry demands more energy- efficient designs. The application-centric design style for these architectures is heavily dependent on workload characterization of intrinsic program characteristics, but at the same time these architectures are likely to be decoupled from legacy ISAs. In this work, we perform ISA-independent workload characterization for a variety of important intrinsic program characteristics relating to computation, memory, and control flow. The analysis is performed using a JIT compiler that emits ISA-independent instructions. We compare this analysis with an x86 trace and find that several of the analyses are highly sensitive to the ISA. We conclude that designers of specialized architectures must adopt ISA-independent workload characterization approaches.}, keywords = {wiica}, url = {https://doi.org/10.1109/ISPASS.2013.6557175}, author = {Yakun Shao and David Brooks} } @article {wood2013flight, title = {Flight of the robobees}, journal = {Scientific American}, volume = {308}, year = {2013}, pages = {60{\textendash}65}, publisher = {Scientific American, a division of Nature America, Inc.}, abstract = {Not too long ago a mysterious affliction called colony collapse disorder (CCD) began to wipe out honeybee hives. These bees are responsible for most commercial pollination in the U.S., and their loss provoked fears that agriculture might begin to suffer as well. In 2009 the three of us, along with colleagues at Harvard University and Northeastern University, began to seriously consider what it would take to create a robotic bee colony. We wondered if mechanical bees could replicate not just an individual{\textquoteright}s behavior but the unique behavior that emerges out of interactions among thousands of bees. We have now created the first RoboBees{\textemdash}flying bee-size robots{\textemdash}and are working on methods to make thousands of them cooperate like a real hive.}, url = {https://ssr.seas.harvard.edu/files/ssr/files/sciam2013-robobee.pdf}, author = {Robert Wood and Nagpal Radhika and Gu Wei} } @article {kanev2013measuring, title = {Measuring code optimization impact on voltage noise}, journal = {Workshop in Silicon Errors {\textendash} System Effects (SELSE)}, year = {2013}, abstract = {In this paper, we characterize the impact of compiler optimizations on voltage noise. While intuition may suggest that the better processor utilization ensured by optimizing compilers results in a small amount of voltage variation, our measurements on a Intel Core2 Duo processor show the opposite {\textendash} the majority of SPEC 2006 benchmarks exhibit more voltage droops when aggressively optimized. We show that this increase in noise could be sufficient for a net performance decrease in a typical-case, resilient design.}, url = {http://www.eecs.harvard.edu/~skanev/papers/selse13vopt.pdf}, author = {Svilen Kanev and Timothy Jones and Gu Wei and David Brooks and Vijay Reddi} } @article {kanev2013measuring, title = {Measuring code optimization impact on voltage noise}, year = {2013}, abstract = {In this paper, we characterize the impact of compiler optimizations on voltage noise. While intuition may suggest that the better processor utilization ensured by optimizing compilers results in a small amount of voltage variation, our measurements on a Intel Core2 Duo processor show the opposite {\textendash} the majority of SPEC 2006 benchmarks exhibit more voltage droops when aggressively optimized. We show that this increase in noise could be sufficient for a net performance decrease in a typical-case, resilient design.}, author = {Svilen Kanev and Timothy Jones and Gu Wei and David Brooks and Vijay Reddi} } @conference {Lee2012, title = {Evaluation of voltage stacking for near-threshold multicore computing}, booktitle = {ISLPED {\textquoteright}12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design}, year = {2012}, pages = {373{\textendash}378https}, abstract = {

This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each other, voltage stacking reduces the chip current draw and simplifies off-chip power delivery but within-die voltage noise due to inter-layer current mismatch is an issue. Results show that unlike conventional power delivery schemes, supply rail impedance in voltage stacked systems depend on aggregate power consumption, leading to better noise immunity for high power (low impedance) operation for many-core processors.

}, keywords = {voltage-stacking}, url = {https://doi.org/10.1145/2333660.2333746}, author = {Sae Lee and David Brooks and Gu Wei} } @conference {kanev2012xiosim, title = {XIOSim: power-performance modeling of mobile x86 cores}, booktitle = {International symposium on Low power Electronics and Design (ISLPED)}, year = {2012}, publisher = {ACM}, organization = {ACM}, abstract = {Simulation is one of the main vehicles of computer architecture research. In this paper, we present XIOSim {\textendash}- a highly detailed microarchitectural simulator targeted at mobile x86 microprocessors. The simulator execution model that we propose is a blend between traditional user-level simulation and full-system simulation. Our current implementation features detailed power and performance core models which allow microarchitectural exploration. Using a novel validation methodology, we show that XIOSim{\textquoteright}s performance models manage to stay well within 10\% of real hardware for the whole SPEC CPU2006 suite. Furthermore, we validate power models against measured data to show a deviation of less than 5\% in terms of average power consumption.}, keywords = {helix}, url = {http://dx.doi.org/10.1145/2333660.2333722}, author = {Svilen Kanev and Gu Wei and David Brooks} } @article {campanoni2012helix, title = {HELIX: Making the extraction of thread-level parallelism mainstream}, journal = {IEEE Micro}, volume = {32}, year = {2012}, pages = {8{\textendash}18}, publisher = {IEEE}, abstract = {Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don{\textquoteright}t parallelize code automatically. Helix automatically parallelizes general-purpose programs without requiring any special hardware; avoids slowing down compiled programs, making it a suitable candidate for mainstream compilers; and outperforms the most similar historical technique that has been implemented in production compilers.}, url = {https://doi.org/10.1109/MM.2012.50}, author = {Simone Campanoni and Timothy Jones and Glenn Holloway and Gu Wei and David Brooks} } @article {campanoni2012making, title = {Making the Extraction of Thread-Level Parallelism Mainstream}, journal = {IEEE Micro}, year = {2012}, publisher = {IEEE}, abstract = {Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still do not parallelize code automatically. Promising parallelization approaches have either required manual programmer assistance, depended on special hardware features, or risked slowing down programs they should have speeded up. HELIX is one such approach that automatically parallelizes general-purpose programs without requiring any special hardware. In this paper we show that in practice HELIX always avoids slowing down compiled programs, making it a suitable candidate for mainstream compilers. We also show experimentally that HELIX outperforms the most similar historical technique that has been implemented in production compilers.}, keywords = {helix}, url = {https://doi.org/10.1109/MM.2012.50}, author = {Simone Campanoni and Timothy Jones and Glenn Holloway and Gu Wei and David Brooks} } @conference {campanoni2012helixb, title = {The HELIX project: overview and directions}, booktitle = {Design Automation Conference (DAC)}, year = {2012}, publisher = {ACM}, organization = {ACM}, address = {San Francisco, CA, USA}, abstract = {Parallelism has become the primary way to maximize processor performance and power efficiency. But because creating parallel programs by hand is difficult and prone to error, there is an urgent need for automatic ways of transforming conventional programs to exploit modern multicore systems. The HELIX compiler transformation is one such technique that has proven effective at parallelizing individual sequential programs automatically for a real six-core processor. We describe that transformation in the context of the broader HELIX research project, which aims to optimize the throughput of a multicore processor by coordinated changes in its architecture, its compiler, and its operating system. The goal is to make automatic parallelization mainstream in multiprogramming settings through adaptive algorithms for extracting and tuning thread-level parallelism.}, keywords = {helix}, url = {https://doi.org/10.1145/2228360.2228412}, author = {Simone Campanoni and Timothy Jones and Glenn Holloway and Gu Wei and David Brooks} } @article {karpelson2012driving, title = {Driving high voltage piezoelectric actuators in microrobotic applications}, journal = {Sensors and actuators A: Physical}, volume = {176}, year = {2012}, pages = {78{\textendash}89}, publisher = {Elsevier}, abstract = {

Piezoelectric actuators have been used successfully to enable locomotion in aerial and ambulatory microrobotic platforms. However, the use of piezoelectric actuators presents two major challenges for power electronic design: generating high-voltage drive signals in systems typically powered by low-voltage energy sources, and recovering unused energy from the actuators. Due to these challenges, conventional drive circuits become too bulky or inefficient in low mass applications. This work describes electrical characteristics and drive requirements of low mass piezoelectric actuators, the design and optimization of suitable drive circuit topologies, aspects of the physical instantiation of these topologies, including the fabrication of extremely lightweight magnetic components, and a custom, ultra low power integrated circuit that implements control functionality for the drive circuits. The principles and building blocks presented here enable efficient high-voltage drive circuits that can satisfy the stringent weight and power requirements of microrobotic applications.

}, url = {https://doi.org/10.1016/j.sna.2011.11.035}, author = {Karpelson, Michael and Gu Wei and Wood,J} } @conference {campanoni2012helix, title = {HELIX: Automatic parallelization of irregular programs for chip multiprocessing}, booktitle = {International Symposium on Code Generation and Optimization (CGO)}, year = {2012}, publisher = {ACM}, organization = {ACM}, abstract = {We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of a loop to separate threads. We show that the inter-thread communication costs forced by loop-carried data dependences can be mitigated by code optimization, by using an effective heuristic for selecting loops to parallelize, and by using helper threads to prefetch synchronization signals. We have implemented HELIX as part of an optimizing compiler framework that automatically selects and parallelizes loops from general sequential programs. The framework uses an analytical model of loop speedups, combined with profile data, to choose loops to parallelize. On a six-core Intel Core i7-980X, HELIX achieves speedups averaging 2.25, with a maximum of 4.12, for thirteen C benchmarks from SPEC CPU2000.}, keywords = {helix}, url = {https://doi.org/10.1145/2259016.2259028}, author = {Simone Campanoni and Timothy Jones and Glenn Holloway and Vijay Reddi and Gu Wei and David Brooks} } @article {chung2012simulated, title = {Simulated-annealing-based adaptive equaliser for on-die variation compensation}, journal = {Electronics letters}, volume = {48}, year = {2012}, pages = {18{\textendash}19}, publisher = {IET}, abstract = {

Fully exploiting the flexibility of lookup-table-based equalisers, it is proposed to compensate for on-die variation effects within a transmit-side equaliser. To efficiently deal with the nonlinear nature of circuit non-idealities, the proposed equaliser utilises simulated annealing for adaptation.

}, url = {https://doi.org/10.1049/el.2011.3016}, author = {Chung, H and Gu Wei} } @article {lyons2012accelerator, title = {The Accelerator Store: a shared memory framework for accelerator-based systems}, journal = {Transactions on Architecture and Code Optimization (TACO)}, year = {2012}, publisher = {ACM}, abstract = {This paper presents the many-accelerator architecture, a design approach combining the scalability of homogeneous multi-core architectures and system-on-chip{\textquoteright}s high performance and power-efficient hardware accelerators. In preparation for systems containing tens or hundreds of accelerators, we characterize a diverse pool of accelerators and find each contains significant amounts of SRAM memory (up to 90\% of their area). We take advantage of this discovery and introduce the accelerator store, a scalable architectural component to minimize accelerator area by sharing its memories between accelerators. We evaluate the accelerator store for two applications and find significant system area reductions (30\%) in exchange for small overheads (2\% performance, 0\%{\textendash}8\% energy). The paper also identifies new research directions enabled by the accelerator store and the many-accelerator architecture.}, keywords = {accelerator-store}, url = {https://doi.org/10.1145/2086696.2086727}, author = {Michael Lyons and Mark Hempstead and Gu Wei and David Brooks} } @article {lyons2012accelerator, title = {The accelerator store: A shared memory framework for accelerator-based systems}, journal = {ACM Transactions on Architecture. and Code Optimization}, volume = {8}, year = {2012}, pages = {1-22}, publisher = {Association for Computing Machinery (ACM)}, abstract = {

This paper presents the many-accelerator architecture, a design approach combining the scalability of homogeneous multi-core architectures and system-on-chip{\textquoteright}s high performance and power-efficient hardware accelerators. In preparation for systems containing tens or hundreds of accelerators, we characterize a diverse pool of accelerators and find each contains significant amounts of SRAM memory (up to 90\% of their area). We take advantage of this discovery and introduce the accelerator store, a scalable architectural component to minimize accelerator area by sharing its memories between accelerators. We evaluate the accelerator store for two applications and find significant system area reductions (30\%) in exchange for small overheads (2\% performance, 0\%--8\% energy). The paper also identifies new research directions enabled by the accelerator store and the many-accelerator architecture.

}, url = {https://doi.org/10.1145/2086696.2086727}, author = {Michael Lyons and Mark Hempstead and Gu Wei and David Brooks} } @conference {tseng2012analytical, title = {Analytical Latency-Throughput Model of Future Power Constrained Multicore Processors}, booktitle = {Workshop on Energy Efficient Design, ISCA}, volume = {600}, year = {2012}, pages = {800}, abstract = {Despite increased core counts that provide significant throughput performance gains, single thread performance is still an important metric in today{\textquoteright}s processor designs. Due to chip power constraints, architects must carefully allocate power budgets to additional cores or increased single thread performance. To study this tradeoff between different performance metrics, we construct an analytical model that computes single thread and throughput performance under a given power budget for both symmetric and asymmetric multicore architectures. We also consider multi-task workloads, where optimal designs might include more than one large core in the heterogeneous architecture. Our analytical model considers the optimal number and complexity of cores in a processor and quantifies the benefits of asymmetric designs when trading latency and throughput. We show that a diverse set of core designs can be optimal in different scenarios.}, author = {Amanda Tseng and David Brooks} } @article {kim2012fully, title = {A fully-integrated 3-level DC-DC converter for nanosecond-scale DVFS}, journal = {Solid-State Circuits, IEEE Journal of}, volume = {47}, year = {2012}, pages = {206{\textendash}219}, publisher = {IEEE}, abstract = {On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77\% peak efficiency at power density of 0.1 W/mm 2 and 63\% efficiency at maximum power density of 0.3 W/mm 2 . The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters.}, url = {https://doi.org/10.1109/JSSC.2011.2169309}, author = {Wonyoung Kim and David Brooks and Gu Wei} } @article {lyons2012shrink, title = {Shrink-Fit: A Framework for Flexible Accelerator Sizing}, journal = {IEEE Computer Architecture Letters}, volume = {12}, year = {2012}, pages = {17 - 20}, publisher = {IEEE}, abstract = {RTL design complexity discouraged adoption of reconfigurable logic in general purpose systems, impeding opportunities for performance and energy improvements. Recent improvements to HLS compilers simplify RTL design and are easing this barrier. A new challenge will emerge: managing reconfigurable resources between multiple applications with custom hardware designs. In this paper, we propose a method to {\textquotedblleft}shrink-fit{\textquotedblright} accelerators within widely varying fabric budgets. Shrink-fit automatically shrinks existing accelerator designs within small fabric budgets and grows designs to increase performance when larger budgets are available. Our method takes advantage of current accelerator design techniques and introduces a novel architectural approach based on fine-grained virtualization. We evaluate shrink-fit using a synthesized implementation of an IDCT for decoding JPEGs and show the IDCT accelerator can shrink by a factor of 16x with minimal performance and area overheads. Using shrink-fit, application designers can achieve the benefits of hardware acceleration with single RTL designs on FPGAs large and small.}, keywords = {accelerator-store}, url = {https://doi.org/10.1109/L-CA.2012.7}, author = {Michael Lyons and Gu Wei and David Brooks} } @conference {lira2011implementing, title = {Implementing a hybrid SRAM/eDRAM NUCA architecture}, booktitle = {High Performance Computing (HiPC), 2011 18th International Conference on}, year = {2011}, pages = {1{\textendash}10}, publisher = {IEEE}, organization = {IEEE}, address = {Bengaluru, India}, abstract = {Advances in technology allowed for integrating DRAM-like structures into the chip, called embedded DRAM (eDRAM). This technology has already been successfully implemented in some GPUs and other graphic-intensive SoC, like game consoles. The most recent processor from IBM {\textregistered} , POWER7, is the first general-purpose processor that integrates an eDRAM module on the chip. In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are evicted. Based on that observation, we propose a placement scheme where re-accessed data blocks are stored in fast, but costly in terms of area and power, SRAM banks, while eDRAM banks store data blo cks that just arrive to the NUCA cache or were demoted from a SRAM bank. We show that a well-balanced SRAM / eDRAM NUCA cache can achieve similar performance results than using a NUCA cache composed of only SRAM banks, but reduces area by 15\% and power consumed by 10\%. Furthermore, we also explore several alternatives to exploit the area reduction we gain by using the hybrid architecture, resulting in an overall performance improvement of 4\%.}, url = {https://doi.org/10.1109/HiPC.2011.6152738}, author = {Javier Lira and Carlos Molina and David Brooks and Antonio Gonzalez} } @article {Reddi2011, title = {Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, volume = {30}, year = {2011}, pages = {1429{\textendash}1445}, publisher = {IEEE}, abstract = {Unintended variations in circuit lithography and undesirable fluctuations in circuit operating parameters such as supply voltage and temperature are threatening the continuation of technology scaling that microprocessor evolution relies on. Although circuit-level solutions for some variation problems may be possible, they are prohibitively expensive and impractical for commodity processors, on which not only the consumer market but also an increasing segment of the business market now depends. Solutions at the microarchitecture level and even the software level, on the other hand, overcome some of these circuit-level challenges without significantly raising costs or lowering performance. Using examples drawn from our Alarms Project and related work, we illustrate how collaborative design that encompasses circuits, architecture, and chip-resident software leads to a cost-effective solution for inductive voltage noise, sometimes called the dI / dt problem. The strategy that we use for assuring correctness while preserving performance can be extended to other variation problems.}, url = {https://doi.org/10.1109/TCAD.2011.2163635}, author = {Vijay Reddi and David Brooks} } @conference {duhamel2011hardware, title = {Hardware in the loop for optical flow sensing in a robotic bee}, booktitle = {Intelligent Robots and Systems (IROS), 2011 IEEE/RSJ International Conference on}, year = {2011}, pages = {1099{\textendash}1106}, publisher = {IEEE}, organization = {IEEE}, address = {San Francisco, CA, USA}, abstract = {The design of autonomous robots involves the development of many complex, interdependent components, including the mechanical body and its associated actuators, sensors, and algorithms to handle sensor processing, control, and high-level task planning. For the design of a robotic bee (RoboBee) it is necessary to optimize across the design space for minimum weight and power consumption to increase flight time; however, the design space of a single component is large, the interconnectedness and tradeoffs across components must be considered, and interdisciplinary collaborations cause different component design timelines. In this work, we show how the development of a hardware in the loop (HWIL) system for a flapping wing microrobot can simplify and accelerate evaluation of a large number of design choices. Specifically, we explore the design space of the visual system including sensor hardware and associated optical flow processing. We demonstrate the utility of the HWIL system in exposing trends on system performance for optical flow algorithm, field of view, sensor resolution, and frame rate. }, url = {https://doi.org/10.1109/IROS.2011.6095160}, author = {Pierre Duhamel and Judson Porter and Benjamin Finio and Geoffrey Barrows and David Brooks and Gu Wei and Robert Wood} } @conference {agrawal2011area, title = {Area efficient phase calibration of a 1.6 GHz multiphase DLL}, booktitle = {2011 IEEE Custom Integrated Circuits Conference (CICC)}, year = {2011}, pages = {1{\textendash}4}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL). The calibration scheme employs sub-sampling using a frequency-offset clock with respect to the DLL reference clock, to measure phase-offsets. The phase-correction circuit uses one digital-to-analog converter across eight variable-delay buffers to reduce the area consumption by 62\%. The test-chip, designed in a 130 nm CMOS process, demonstrates a 8-phase 1.6 GHz DLL with a worst-case phase error of 450 fs.}, url = {https://doi.org/10.1109/CICC.2011.6055345}, author = {Agrawal, Ankur and Hanumolu, Kumar and Gu Wei} } @article {brooks2011cpus, title = {CPUs, GPUs, and Hybrid Computing}, journal = {IEEE Micro}, year = {2011}, pages = {4{\textendash}6}, publisher = {Published by the IEEE Computer Society}, abstract = {This introduction to the special issue discusses advances and challenges in the field of hybrid CPU/GPU computing.}, url = {http://dx.doi.org/10.1109/MM.2011.85}, author = {David Brooks} } @conference {chung2011design, title = {Design considerations for ADC-based backplane receivers}, booktitle = {2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)}, year = {2011}, pages = {1{\textendash}4}, publisher = {IEEE}, organization = {IEEE}, abstract = {High-speed ADC-based backplane receivers often suffer from high power consumption and complexity and require careful designs. This paper discusses circuit- and system-level design considerations for such receivers. A low-power, high-speed front-end ADC circuit and a high-level design-space exploration of ADC-based receivers are presented.}, url = {https://doi.org/10.1109/MWSCAS.2011.6026280}, author = {Chung, Hayun and Gu Wei} } @article {hempstead2011accelerator, title = {An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS}, journal = {Emerging and Selected Topics in Circuits and Systems, IEEE Journal on}, volume = {1}, year = {2011}, pages = {193{\textendash}202}, publisher = {IEEE}, abstract = {Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Reducing power consumption requires the development of system-on-chip implementations that must provide both energy efficiency and adequate performance to meet the demands of the long deployment lifetimes and bursts of computation that characterize wireless sensor network (WSN) applications. Therefore, this work argues that designers should evaluate the design in terms of average power for an entire workload, including active and idle periods, not just the metric of energy-per-instruction.}, url = {http://dx.doi.org/10.1109/JETCAS.2011.2160751}, author = {Mark Hempstead and David Brooks and Gu Wei} } @conference {karpelson2011low, title = {Low power control IC for efficient high-voltage piezoelectric driving in a flying robotic insect}, booktitle = {2011 Symposium on VLSI Circuits-Digest of Technical Papers}, year = {2011}, pages = {178{\textendash}179}, publisher = {IEEE}, organization = {IEEE}, abstract = {A dual-channel, low power control IC for driving high voltage piezoelectric actuators in a flapping-wing robotic insect is presented. The IC controls milligram-scale power electronics that meet the stringent weight and power requirements of aerial microrobots. Designed in a 0.13{\textmu}m CMOS process, the IC implements an efficient control algorithm to drive piezoelectric actuators with high temporal resolution while consuming <100{\textmu}W during normal operation at 1.0V. Keywords: low power, SOC, high voltage, piezoelectric actuator, and microrobotics.}, author = {Karpelson, Michael and Wood, Robert J and Gu Wei} } @conference {bailis2011dimetrodon, title = {Dimetrodon: processor-level preventive thermal management via idle cycle injection}, booktitle = {Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE}, year = {2011}, pages = {89{\textendash}94}, publisher = {IEEE}, organization = {IEEE}, address = {San Diego, CA, USA}, abstract = {Processor-level dynamic thermal management techniques have long targeted worst-case thermal margins. We examine the thermal-performance trade-offs in average-case, preventive thermal management by actively degrading application performance to achieve long-term thermal control. We propose Dimetrodon, the use of idle cycle injection, a flexible, per-thread technique, as a preventive thermal management mechanism and demonstrate its efficiency compared to hardware techniques in a commodity operating system on real hardware under throughput and latency-sensitive real-world workloads. Compared to inflexible hardware techniques, Dimetrodon achieves favorable trade-offs for temperature reductions up to 30\% due to rapid heat dissipation during short idle intervals.}, author = {Peter Bailis and Vijay Reddi and Sanjay Gandhi and David Brooks and Margo Seltzer} } @conference {karpelson2011design, title = {Design and fabrication of ultralight high-voltage power circuits for flapping-wing robotic insects}, booktitle = {2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)}, year = {2011}, pages = {2070{\textendash}2077}, publisher = {IEEE}, organization = {IEEE}, abstract = {Flapping-wing robotic insects are small, highly maneuverable flying robots inspired by biological insects and useful for a wide range of tasks, including exploration, environmental monitoring, search and rescue, and surveillance. Recently, robotic insects driven by piezoelectric actuators have achieved the important goal of taking off with external power; however, fully autonomous operation requires an ultralight power supply capable of generating high-voltage drive signals from low-voltage energy sources. This paper describes high-voltage switching circuit topologies and control methods suitable for driving piezoelectric actuators in flapping-wing robotic insects and discusses the physical implementation of these topologies, including the fabrication of custom magnetic components by laser micromachining and other weight minimization techniques. The performance of laser micromachined magnetics and custom-wound commercial magnetics is compared through the experimental realization of a tapped inductor boost converter capable of stepping up a 3.7V Li-poly cell input to 200V. The potential of laser micromachined magnetics is further shown by implementing a similar converter weighing 20mg (not including control functionality) and capable of up to 70mW output at 200V and up to 100mW at 100V.}, url = {https://doi.org/10.1109/APEC.2011.5744882}, author = {Karpelson, Michael and Whitney P and Gu Wei and Wood J} } @article {brownell2011automating, title = {Automating design of voltage interpolation to address process variations}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, year = {2011}, pages = {1{\textendash}14}, publisher = {IEEE}, abstract = {

Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed post-fabrication tuning knob called voltage interpolation. Successful implementation of this technique requires examination of the design tradeoffs between circuit tuning range and static power overheads within the synthesis flow of the design process, in addition to the implications of place and route. Results from the exploration of the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks show that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. A design using voltage interpolation can match the nominal delay target with a 16\% power cost, or for the same power budget, incur only a 13\% delay overhead after variations.

}, url = {https://doi.org/10.1109/TVLSI.2009.2034457}, author = {Kevin Brownell and Ali Khan and Gu Wei and David Brooks} } @conference {Kim2011, title = {A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation}, booktitle = {IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)}, year = {2011}, pages = {268{\textendash}270}, publisher = {IEEE}, organization = {IEEE}, abstract = {In recent years, chip multiprocessor architectures have emerged to scale performance while staying within tight power constraints. This trend motivates per core/block dynamic voltage and frequency scaling (DVFS) with fast voltage transition. Given the high cost and bulk of off-chip DC/DC converters to implement multiple on-chip power domains, there has been a surge of interest in on-chip converters. This paper presents the design and experimental results of a fully integrated 3-level DC/DC converter that merges characteristics of both inductor-based buck and switched-capacitor (SC) converters. While off-chip buck converters show high conversion efficiency, their on-chip counterparts suffer from loss due to low quality inductors. With the help of flying capacitors, the 3-level converter requires smaller inductors than the buck converter, reducing loss and on-die area overhead. Compared to SC converters that need more com plex structures to regulate higher than half the input voltage, 3-level converters can efficiently regulate the output voltage across a wide range of levels and load currents. Measured results from a 130nm CMOS test-chip prototype demon strate nanosecond-scale voltage transition times and peak conversion efficiency of 77\%.}, url = {https://doi.org/10.1109/ISSCC.2011.5746313}, author = {Wonyoung Kim and David Brooks and Gu Wei} } @conference {rangan2011achieving, title = {Achieving uniform performance and maximizing throughput in the presence of heterogeneity}, booktitle = {High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on}, year = {2011}, pages = {3{\textendash}14}, publisher = {IEEE}, organization = {IEEE}, abstract = {Continued scaling of process technologies is critical to sustaining improvements in processor frequencies and performance. However, shrinking process technologies exacerbates process variations - the deviation of process parameters from their target specifications. In the context of multi-core CMPs, which are implemented to feature homogeneous cores, within-die process variations result in substantially different core frequencies. Exposing such process-variation induced heterogeneity interferes with the norm of marketing chips at a single frequency. Further, application performance is undesirably dictated by the frequency of the core it is running on. To work around these challenges, a single uniform frequency, dictated by the slowest core, is currently chosen as the chip frequency sacrificing the increased performance capabilities of cores that could operate at higher frequencies. In this paper, we propose choosing the mean frequency across all cores, in lieu of the minimum frequency, as the single-frequency to use as the chip sales frequency. We examine several scheduling algorithms implemented below the O/S in hardware/firmware that guarantee minimum application performance near that of the average frequency, by masking process-variation induced heterogeneity from the end-user. We show that our Throughput-Driven Fairness (TDF) scheduling policy improves throughput by an average of 12\% compared to a naive fairness scheme (round-robin) for frequency-sensitive applications. At the same time, TDF allows 98\% of chips to maintain minimum performance at or above 90\% of that expected at the mean frequency, providing a single uniform performance level to present for the chip.}, url = {https://doi.org/10.1109/HPCA.2011.5749712}, author = {Krishna Rangan and Michael Powell and Gu Wei and David Brooks} } @conference {brooks2011alarms, title = {The alarms project: a hardware/software approach to addressing parameter variations}, booktitle = {Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific}, year = {2011}, pages = {291{\textendash}291}, publisher = {IEEE}, organization = {IEEE}, abstract = {Parameter variations (process, voltage, and temperature) threaten continued performance scaling of power-constrained computer systems. As designers seek to contain the power consumption of microprocessors through reductions in supply voltage and power-saving techniques such as clock-gating, these systems suffer increasingly large power supply fluctuations due to the finite impedance of the power supply network. These supply fluctuations, referred to as voltage emergencies, must be managed to guarantee correctness. Traditional approaches to address this problem incur high-cost or compromise power/performance efficiency. Our research seeks ways to handle these alarm conditions through a combined hardware/software approach, motivated by root cause analysis of voltage emergencies revealing that many of these events are heavily linked to both program control flow and microarchitectural events (cache misses and pipeline flushes). This talk will discuss three aspects of the project: (1) a fail-safe mechanism that provides hardware guaranteed correctness; (2) a voltage emergency predictor that leverages control flow and microarchitectural event information to predict voltage emergencies up to 16 cycles in advance; and (3) a proof-of-concept dynamic compiler implementation that demonstrates that dynamic code transformations can be used to eliminate voltage emergencies from the instruction stream with minimal impact on performance [1{\textendash}9].}, url = {https://dl.acm.org/doi/10.5555/1950815.1950880}, author = {David Brooks} } @article {reddi2011voltage, title = {Voltage Noise in Production Processors}, journal = {IEEE Micro}, volume = {31}, year = {2011}, publisher = {IEEE}, abstract = {Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implications of resilient architecture design for voltage variation in future systems.}, url = {https://doi.org/10.1109/MM.2010.104}, author = {Vijay Reddi and Svilen Kanev and Wonyoung Kim and Simone Campanoni and Michael Smith and Gu Wei and David Brooks} } @conference {reddi2010voltage, title = {Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling}, booktitle = {2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture}, year = {2010}, publisher = {IEEE}, organization = {IEEE}, abstract = {Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-threaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4\%, far from the processor{\textquoteright}s 14\% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today{\textquoteright}s processors, such resilient designs could yield 15\% to 20\% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.}, keywords = {voltage-noise}, url = {https://doi.org/10.1109/MICRO.2010.35}, author = {Vijay Reddi and Svilen Kanev and Wonyoung Kim and Simone Campanoni and Michael Smith and Gu Wei and David Brooks} } @conference {karpelson2010energetics, title = {Energetics of flapping-wing robotic insects: towards autonomous hovering flight}, booktitle = {2010 IEEE/RSJ International Conference on Intelligent Robots and Systems}, year = {2010}, pages = {1630{\textendash}1637}, publisher = {IEEE}, organization = {IEEE}, abstract = {Flapping-wing mechanisms inspired by biological insects have the potential to enable a new class of small, highly maneuverable aerial robots with hovering capabilities. In order for such devices to operate without an external power source, it is necessary to address a complex system design challenge: the integration of all of the required components on board the robot. This paper discusses the flight energetics of flapping-wing robotic insects with the goal of selecting design parameters that enable power autonomy and maximize flight time. The subsystems of the robot are analyzed both from a broad perspective and using a detailed set of models for a piezoelectrically driven two-wing design. The models are used to perform a system-level optimization for the maximum flight time permitted by current technology, compare the resulting robot configurations to biological insects across several key metrics, and discuss the effect of performance gains in various subsystems of the robot.}, url = {https://doi.org/10.1109/IROS.2010.5650269}, author = {Karpelson Michael and Whitney P and Gu Wei and Wood J} } @article {lee2010applied, title = {Applied inference: Case studies in microarchitectural design}, journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, volume = {7}, year = {2010}, pages = {8}, publisher = {ACM}, abstract = {

We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimization. This paradigm enables more comprehensive design studies by combining spatial sampling and statistical inference. Specifically, this paradigm (i) defines a large, comprehensive design space, (ii) samples points from the space for simulation, and (iii) constructs regression models based on sparse simulations. This approach greatly improves the computational efficiency of microarchitectural simulation and enables new capabilities in design space exploration.

We illustrate new capabilities in three case studies for a large design space of approximately 260,000 points: (i) Pareto frontier, (ii) pipeline depth, and (iii) multiprocessor heterogeneity analyses. In particular, regression models are exhaustively evaluated to identify Pareto optimal designs that maximize performance for given power budgets. These models enable pipeline depth studies in which all parameters vary simultaneously with depth, thereby more effectively revealing interactions with nondepth parameters. Heterogeneity analysis combines regression-based optimization with clustering heuristics to identify efficient design compromises between similar optimal architectures. These compromises are potential core designs in a heterogeneous multicore architecture. Increasing heterogeneity can improve\ bips3/w\ efficiency by as much as 2.4{\texttimes}, a theoretical upper bound on heterogeneity benefits that neglects contention between shared resources as well as design complexity. Collectively these studies demonstrate regression models{\textquoteright} ability to expose trends and identify optima in diverse design regions, motivating the application of such models in statistical inference for more effective use of modern simulator infrastructure.

}, url = {https://doi.org/10.1145/1839667.1839670}, author = {Benjamin Lee and David Brooks} } @article {reddi2010eliminating, title = {Eliminating voltage emergencies via software-guided code transformations}, journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, volume = {7}, year = {2010}, pages = {1-28}, publisher = {ACM}, abstract = {In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These fluctuations result from the natural variation of processor activity as workloads execute, but when left unattended, these voltage fluctuations can lead to timing violations or even transistor lifetime issues. In this paper, we present a hardware-software collaborative approach to mitigate voltage fluctuations. A checkpoint-recovery mechanism rectifies errors when voltage violates maximum tolerance settings, while a run-time software layer reschedules the program{\textquoteright}s instruction stream to prevent recurring violations at the same program location. The run-time layer, combined with the proposed code rescheduling algorithm, removes 60\% of all violations with minimal overhead, thereby significantly improving overall performance. Our solution is a radical departure from the ongoing industry standard approach to circumvent the issue altogether by optimizing for the worst case voltage flux, which compromises power and performance efficiency severely, especially looking ahead to future technology generations. Existing conservative approaches will have severe implications on the ability to deliver efficient microprocessors. The proposed technique reassembles a traditional reliability problem as a runtime performance optimization problem, thus allowing us to design processors for typical case operation by building intelligent algorithms that can prevent recurring violations.}, keywords = {voltage-noise}, url = {https://doi.org/10.1145/1839667.1839674}, author = {Vijay Reddi and Simone Campanoni and Meeta Gupta and Michael Smith and Gu Wei and David Brooks and Kim Hazelwood} } @article {calhoun2010can, title = {Can Subthreshold and Near-Threshold Circuits Go Mainstream?}, journal = {Micro, IEEE}, volume = {30}, year = {2010}, pages = {80{\textendash}85}, publisher = {IEEE}, abstract = {Recent research has shown the potential benefits of subthreshold or near-threshold operation, which gives up a substantial degree of speed in order to reduce energy per operation. This is an excellent trade-off for many tasks, such as cyberphysical systems. This prolegomenon summarizes the benefits and challenges of subthreshold or near-threshold operation.}, url = {https://doi.org/10.1109/MM.2010.60}, author = {Benton Calhoun and David Brooks} } @proceedings {shaopower, title = {Power, Performance and Portability: System Design Considerations for Micro Air Vehicle Applications}, year = {2010}, abstract = {Recent years have seen an increased interest in Micro Air Vehicles (MAVs) with applications ranging from search-and-rescue to mimicking insect behavior. MAVs have several challenging design requirements that impact processor design. These include real time processing demands and severe power/weight budgets. In this paper, we describe the characteristics of MAV applications and propose hardware acceleration to improve the power, performance, and portability of MAV system designs.}, url = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.367.5142}, author = {Yakun Sophia Shao and Judson Porter and Michael Lyons and Gu-Yeon Wei and David Brooks} } @patent {liang2010process, title = {Process variation tolerant circuit with voltage interpolation and variable latency}, year = {2010}, note = {US Patent 7,667,497}, edition = {United States of America}, chapter = {US}, abstract = {A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits. The first voltage differs from the second voltage and the plurality of pipelined stages interpolates between the first and second voltages to provide differing effective voltages between the first and second voltages.}, url = {https://doi.org/10.1109/ISSCC.2008.4523228}, author = {Xiaoyao Liang and David Brooks and Gu Wei} } @article {lyons2010accelerator, title = {The Accelerator Store framework for high-performance, low-power accelerator-based systems}, journal = {IEEE Computer Architecture Letters}, volume = {9}, year = {2010}, pages = {53-56}, publisher = {IEEE}, abstract = {Hardware acceleration can increase performance and reduce energy consumption. To maximize these benefits, accelerator- based systems that emphasize computation on accelerators (rather than on general purpose cores) should be used. We introduce the {\textquotedblleft}accelerator store,{\textquotedblright} a structure for sharing memory between accelerators in these accelerator-based systems. The accelerator store simplifies accelerator I/O and reduces area by mapping memory to accelerators when needed at runtime. Preliminary results demonstrate a 30\% system area reduction with no energy overhead and less than 1\% performance overhead in contrast to conventional DMA schemes.}, keywords = {accelerator-store}, url = {https://doi.org/10.1109/L-CA.2010.16}, author = {Michael Lyons and Mark Hempstead and Gu Wei and David Brooks} } @article {reddi2010predicting, title = {Predicting voltage droops using recurring program and microarchitectural event activity}, journal = {IEEE Micro}, volume = {30}, year = {2010}, publisher = {IEEE}, abstract = {Shrinking feature size and diminishing supply voltage are making circuits more sensitive to supply voltage fluctuations within a microprocessor. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues. A mechanism that dynamically learns to predict dangerous voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger.}, keywords = {voltage-noise}, url = {https://doi.org/10.1109/MM.2010.25}, author = {Vijay Reddi and Meeta Gupta and Glenn Holloway and Michael Smith and Gu Wei and David Brooks} } @conference {gupta2009tribeca, title = {Tribeca: design for PVT variations with local recovery and fine-grained adaptation}, booktitle = {2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)}, year = {2009}, pages = {435{\textendash}446}, publisher = {IEEE}, organization = {IEEE}, address = {New York, NY, USA}, abstract = {

With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing margins of the design - degrading performance significantly. Because runtime variations like supply voltage droops and temperature fluctuations depend on the activity signature of the processor{\textquoteright}s workload, there are several opportunities to improve performance by dynamically adapting margins. This paper explores the power-performance efficiency gains that result from designing for typical conditions while dynamically tuning frequency and voltage to accommodate the runtime behavior of workloads. Such a design depends on a fail-safe mechanism that allows it to protect against margin violations during adaptation; we evaluate several such mechanisms, and we propose a local recovery scheme that exploits spatial variation among the units of the processor. While a processor designed for worst-case conditions might only be capable of a frequency that is 75\% of an ideal processor with no parameter variations, we show that a fine-grained global frequency tuning mechanism improves power-performance efficiency (BIPS\ 3\ /W) by 40\% while operating at 91\% of an ideal processor{\textquoteright}s frequency. Moreover, a per-unit voltage tuning mechanism aims to reduce the effect of within-die spatial variations to provide a 55\% increase in power-performance efficiency. The benefits reported are clearly substantial in light of the \<1\% area overhead relative to existing global recovery mechanisms.

}, url = {https://doi.org/10.1145/1669112.1669168}, author = {Meeta Gupta and Jude Rivers and Pradip Bose and Gu Wei and David Brooks} } @conference {lovin2009empirical, title = {Empirical performance models for 3T1D memories}, booktitle = {ICCD{\textquoteright}09: Proceedings of the 2009 IEEE international conference on Computer design}, year = {2009}, pages = {398{\textendash}403}, publisher = {IEEE}, organization = {IEEE}, abstract = {Process variation poses a threat to the performance and reliability of the 6T SRAM cell. Research has turned to new memory cell designs, such as the 3T1D DRAM cell, as potential replacement designs. If designers are to consider 3T1D memory architectures, performance models are needed to better understand memory cell behavior. We propose a decoupled approach for collecting Monte Carlo HSPICE data, reducing simulation times by simulating memory array components separately based on their contribution to the worst-case critical path. We use this Monte Carlo data to train regression models, which accurately predict retention and access times of a 3T1D memory array with a median error of 7.39\%.}, author = {Kristen Lovin and Benjamin Lee and Xiaoyao Liang and David Brooks and Gu Wei} } @conference {chung2009design, title = {Design-space exploration of backplane receivers with high-speed ADCs and digital equalization}, booktitle = {2009 IEEE Custom Integrated Circuits Conference}, year = {2009}, pages = {555{\textendash}558}, publisher = {IEEE}, organization = {IEEE}, abstract = {High-speed backplane receivers based on front-end ADCs with digital equalization facilitate design reuse, portability, and flexibility to reconfigure itself and accommodate different channel environments. However, power and complexity of such receivers can be high and require thorough high-level exploration to optimize design tradeoffs. This paper presents a backplane receiver model consisting of a simple, accurate, experimentally-verified, and parameterized high-speed flash ADC and a configurable digital equalizer for design-space exploration. Simulations demonstrate tradeoffs between ADC and equalizer bit resolution while maintaining constant receiver performance.}, url = {https://doi.org/10.1109/CICC.2009.5280767}, author = {Chung Hayun and Gu Wei} } @article {agrawal20098, title = {An 8$, times, $5 Gb/s Parallel Receiver With Collaborative Timing Recovery}, journal = {IEEE Journal of Solid-State Circuits}, volume = {44}, year = {2009}, pages = {3120{\textendash}3130}, publisher = {IEEE}, abstract = {This paper presents the design of an 8 channel, 5 \& Gb/s per channel parallel receiver with collaborative timing recovery and no forwarded clock. The receiver architecture exploits synchrony in the transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. This collaborative timing recovery scheme enables wideband jitter tracking without increasing the dithering jitter in the synthesized clock. Circuit design techniques employed to implement this receiver architecture are discussed. Experimental results from a 130 nm CMOS test chip demonstrate the enhanced tracking bandwidth and lower dithering jitter of the recovered clock.}, url = {https://doi.org/10.1109/JSSC.2009.2033399}, author = {Agrawal, Ankur and Liu, Andrew and Hanumolu, Pavan Kumar and Gu-Yeon Wei} } @conference {lyons2009design, title = {The design of a bloom filter hardware accelerator for ultra low power systems}, booktitle = {ISLPED {\textquoteright}09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design (ISLPED)}, year = {2009}, pages = {371{\textendash}376https}, publisher = {ACM}, organization = {ACM}, abstract = {Battery-powered embedded systems require low energy usage to extend system lifetime. These systems must power many components for long periods of time and are particularly sensitive to energy use. Recent techniques for reducing energy consumption in wireless sensor networks, such as aggregation, require additional computation to reduce energy intensive radio transmissions. Larger demands on the processor will require more computational energy, but traditional energy reduction approaches, such as multi-core scaling with reduced frequency and voltage may prove heavy handed and ineffective for motes (sensor network nodes). Alternatively, application-specific hardware design (ASHD) architectures can reduce computational energy consumption by processing operations common to specific applications more efficiently than a general purpose processor. By the nature of their deeply embedded operation, motes support a limited set of applications, and thus the conventional general purpose computing paradigm may not be well-suited to mote operation. This paper examines the design considerations of a hardware accelerator for compressed Bloom filters, a data structure for efficiently storing set membership. We evaluate our ASHD design for three representative wireless sensor network applications and demonstrate that ASHD design reduces network latency by 59\% and computational energy by 98\%, showing the need for architecting processors for ASHD accelerators.}, url = {https://doi.org/10.1145/1594233.1594330}, author = {Michael Lyons and David Brooks} } @conference {reddi2009software, title = {Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack}, booktitle = {2009 46th ACM/IEEE Design Automation Conference}, year = {2009}, pages = {788{\textendash}793}, publisher = {IEEE}, organization = {IEEE}, address = {San Francisco, CA}, abstract = {Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-time software layer reschedules the program{\textquoteright}s instruction stream to prevent recurring margin crossings at the same program location. The run-time layer removes 60\% of these events with minimal overhead, thereby significantly improving overall performance.}, url = {https://doi.org/10.1145/1629911.1630114}, author = {Vijay Reddi and Meeta Gupta and Michael Smith and Gu Wei and David Brooks and Simone Campanoni} } @conference {reddi2009software, title = {Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack}, booktitle = {Proceedings of the 46th Annual Design Automation Conference}, year = {2009}, pages = {788{\textendash}793}, address = {San Francisco, CA}, abstract = {Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-time software layer reschedules the program{\textquoteright}s instruction stream to prevent recurring margin crossings at the same program location. The run-time layer removes 60\% of these events with minimal overhead, thereby significantly improving overall performance.}, url = {https://doi.org/10.1145/1629911.1630114}, author = {Vijay Reddi and Meeta Gupta and Michael Smith and Gu Wei and David Brooks and Simone Campanoni} } @conference {chung20097, title = {A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS}, booktitle = {2009 Symposium on VLSI Circuits}, year = {2009}, pages = {268{\textendash}269}, publisher = {IEEE}, organization = {IEEE}, address = {Kyoto, Japan}, abstract = {

A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low power consumption. The 7.5-GS/s flash ADC consumes 52-mW and occupies 0.01-mm\ 2\ . Clock duty cycle control improves ENOB from 3.5 to 3.8 with an input sinusoid at the Nyquist frequency.

}, url = {https://ieeexplore.ieee.org/abstract/document/5205316/similar$\#$similar}, author = {Chung, Hayun and Rylyakov, Alexander and Deniz, Toprak and Bulzacchelli, John and Gu Wei and Friedman Daniel} } @conference {rangan2009thread, title = {Thread motion: fine-grained power management for multi-core systems}, booktitle = {ACM SIGARCH Computer Architecture News}, volume = {37}, year = {2009}, pages = {302{\textendash}313}, publisher = {ACM}, organization = {ACM}, edition = {3}, abstract = {

Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management scheme that dynamically adjusts power and performance to the time-varying needs of running programs. Unfortunately, conventional DVFS, relying on off-chip regulators, faces limitations in terms of temporal granularity and high costs when considered for future multi-core systems. To overcome these challenges, this paper presents thread motion (TM), a fine-grained power-management scheme for chip multiprocessors (CMPs). Instead of incurring the high cost of changing the voltage and frequency of different cores, TM enables rapid movement of threads to adapt the time-varying computing needs of running applications to a mixture of cores with fixed but different power/performance levels. Results show that for the same power budget, two voltage/frequency levels are sufficient to provide performance gains commensurate to idealized scenarios using per-core voltage control. Thread motion extends workload-based power management into the nanosecond realm and, for a given power budget, provides up to 20\% better performance than coarse-grained DVFS.

}, url = {https://doi.org/10.1145/1555815.1555793}, author = {Krishna Rangan and Gu Wei and David Brooks} } @conference {karpelson2009milligram, title = {Milligram-scale high-voltage power electronics for piezoelectric microrobots}, booktitle = {2009 IEEE international conference on robotics and automation}, year = {2009}, pages = {2217{\textendash}2224}, publisher = {IEEE}, organization = {IEEE}, abstract = {

Compact yet powerful actuators are vital in many robotic applications, particularly small-scale autonomous systems such as bio-inspired microrobots. In recent years, a number of actuation methods have been proposed or applied in a microrobotic context, including piezoelectric [1], electrostatic [2], and dielectric elastomer actuators [3]. These actuation methods have the potential to achieve high efficiencies and power densities in very small geometries. Piezoelectric actuators in particular have shown promise in applications with very stringent weight and power density requirements, such as the Harvard Microrobotic Fly (HMF){\textemdash}a flapping-wing robotic insect capable of liftoff with external power [4].

In order to produce mechanical output, the actuation methods mentioned above rely on the presence of electric charge on various electrodes in order to either generate high electric fields, as in the case of piezoelectric actuators, or high electrostatic forces, as in the case of electrostatic and dielectric elastomer actuators. Moreover, the geometries of such actuators inherently produce significant electrical capacitance, and therefore high operating voltages are usually necessary to accumulate a sufficient amount of charge on the actuator electrodes, ranging from tens to thousands of volts. For example, the piezoelectric actuators used in the HMF require drive voltages in the range of 200{\textendash}300V. There are two major challenges in the design of power electronics capable of driving capacitive actuators: generating high voltages from low-voltage sources and recovering unused energy from the actuator.

Most compact energy sources suitable for microrobotic applications, such as lithium batteries, supercapacitors [5], solar cells [6], and fuel cells [7], generate output voltages below 5V. Connecting many such cells in series to obtain high voltage is generally not practical because the packaging overhead causes a significant reduction in energy density. Consequently, the generation of high voltages for HMF actuators requires voltage conversion circuits with step-up ratios ranging from 50 to 100. While there are a number of circuit topologies with high step-up ratios, many of them cannot be easily miniaturized and/or suffer from poor efficiency at the low output power levels common in microrobotic applications. Careful selection and optimization of the conversion circuit is necessary to ensure that heavy, inefficient electronics do not compromise system performance.

In addition to the voltage step-up functionality, the power electronics circuitry must generate a time-varying signal on the input electrodes of the actuator. The second challenge stems from the fact that, depending on the properties of the actuator, the nature of the mechanical load, and the characteristics of the drive signal, only a small fraction of the electrical energy stored in the actuator is converted into useful mechanical output [8]. In order to maximize overall system efficiency, it is highly desirable to both generate an appropriate drive signal and recover as much of the unused energy as possible, which imposes additional requirements on the drive circuitry.

This paper describes promising power electronics circuits that can generate the high, time-varying voltages necessary for the operation of piezoelectric actuators, while meeting the stringent weight requirements of microrobotic systems and maximizing system efficiency. Although the analysis focuses on piezoelectric actuators, many of the concepts described here can easily be adapted to other high-voltage capacitive actuators, such as electrostatic comb drives or dielectric elastomer actuators. This work reviews the electrical properties and drive requirements of piezoelectric actuators (Section II), and presents power electronics circuits applicable to various types and configurations of piezoelectric actuators (Sections III and IV). Experimental realizations of the drive circuits are described (Section V), including applications to milligram-scale microrobots, such as flapping-wing robotic insects.

}, url = {https://doi.org/10.1109/ROBOT.2009.5152319}, author = {Karpelson, Michael and Gu Wei and Wood J} } @conference {gupta2009event, title = {An event-guided approach to reducing voltage noise in processors}, booktitle = {Design, Automation \&amp; Test in Europe Conference \&amp; Exhibition, 2009. DATE{\textquoteright}09.}, year = {2009}, pages = {160{\textendash}165}, publisher = {IEEE}, organization = {IEEE}, address = {Nice, France}, url = {https://doi.org/10.1109/DATE.2009.5090651}, author = {Meeta Gupta and Vijay Reddi and Glenn Holloway and Gu Wei and David Brooks} } @conference {brownell2009place, title = {Place and route considerations for voltage interpolated designs}, booktitle = {Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design}, year = {2009}, pages = {594{\textendash}600}, publisher = {IEEE}, organization = {IEEE}, abstract = {

Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.

}, url = {https://doi.org/10.1109/ISQED.2009.4810361}, author = {Kevin Brownell and Ali Khan and David Brooks and Gu Wei} } @article {strozek2009energy, title = {Energy-and area-efficient architectures through application clustering and architectural heterogeneity}, journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, volume = {6}, year = {2009}, pages = {4}, publisher = {ACM}, abstract = {

Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This work explores the benefits of architectural customization for a class of embedded architectures typically used in energy- and area-constrained application domains, such as sensor nodes and multimedia processing. We implement a process flow that performs an automatic synthesis and evaluation of the different architectures based on runtime profiles of applications and determines an efficient architecture, with consideration for both energy and area constraints. An expressive architectural model, used by our engine, is introduced that takes advantage of efficient opcode allocation, several memory addressing modes, and operand types. By profiling embedded benchmarks from a variety of sensor and multimedia applications, we show that the energy savings resulting from various architectural optimizations relative to the base architectures (e.g., MIPS and MSP430) are significant and can reach 50\%, depending on the application. We then identify the set of architectures that achieves near-optimal savings for a group of applications. Finally, we propose the use of heterogeneous ISA processors implementing those architectures as a solution to capitalize on energy savings provided by application customization while executing a range of applications efficiently.

}, url = {https://doi.org/10.1145/1509864.1509868}, author = {Lukasz Strozek and David Brooks} } @conference {reddi2009voltage, title = {Voltage emergency prediction: Using signatures to reduce operating margins}, booktitle = {2009 IEEE 15th International Symposium on High Performance Computer Architecture}, year = {2009}, pages = {18{\textendash}29}, publisher = {IEEE}, organization = {IEEE}, address = {Raleigh, NC, USA}, abstract = {Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations in supply voltage means that timing margins throughout the processor must be set pessimistically to protect against worst-case droops and surges. While sensor-based reactive schemes have been proposed to deal with voltage noise, inherent sensor delays limit their effectiveness. Instead, this paper describes a voltage emergency predictor that learns the signatures of voltage emergencies (the combinations of control flow and microarchitectural events leading up to them) and uses these signatures to prevent recurrence of the corresponding emergencies. In simulations of a representative superscalar microprocessor in which fluctuations beyond 4\% of nominal voltage are treated as emergencies (an aggressive configuration), these signatures can pinpoint the likelihood of an emergency some 16 cycles ahead of time with 90\% accuracy. This lead time allows machines to operate with much tighter voltage margins (4\% instead of 13\%) and up to 13.5\% higher performance, which closely approaches the 14.2\% performance improvement possible with an ideal oracle-based predictor.}, url = {10.1109/HPCA.2009.4798233}, author = {Vijay Reddi and Meeta Gupta and Glenn Holloway and Gu Wei and Michael Smith and David Brooks} } @conference {reddivoltage, title = {Voltage emergency prediction: Using Signatures to Reduce Operating Margins}, booktitle = {2009 IEEE 15th International Symposium on High Performance Computer Architecture}, year = {2009}, abstract = {

Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations in supply voltage means that timing margins throughout the processor must be set pessimistically to protect against worst-case droops and surges. While sensor-based reactive schemes have been proposed to deal with voltage noise, inherent sensor delays limit their effectiveness. Instead, this paper describes a voltage emergency predictor that learns the signatures of voltage emergencies (the combinations of control flow and microarchitectural events leading up to them) and uses these signatures to prevent recurrence of the corresponding emergencies. In simulations of a representative superscalar microprocessor in which fluctuations beyond 4\% of nominal voltage are treated as emergencies (an aggressive configuration), these signatures can pinpoint the likelihood of an emergency some 16 cycles ahead of time with 90\% accuracy. This lead time allows machines to operate with much tighter voltage margins (4\% instead of 13\%) and up to 13.5\% higher performance, which closely approaches the 14.2\% performance improvement possible with an ideal oracle-based predictor.

}, url = {https://doi.org/10.1109/HPCA.2009.4798233}, author = {Vijay Reddi and Meeta Gupta and Glenn Holloway and Michael Smith and Gu-Yeon Wei and David Brooks} } @article {reddi2009voltageb, title = {Voltage noise: Why it{\textquoteright}s bad, and what to do about it}, journal = {5th IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE), Palo Alto, CA}, year = {2009}, publisher = {Citeseer}, abstract = {Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose hardware-software collaboration to enable aggressive voltage margins: a fail-safe hardware mechanism tolerates margin violations in order to train a run-time software layer that reschedules instructions to avoid recurring violations. Additionally, the software controls an emergency signature-based predictor that throttles to suppress emergencies that code rescheduling cannot eliminate.}, author = {Vijay Reddi and Meeta Gupta and Krishna Rangan and Simone Campanoni and Glenn Holloway and Michael Smith and Gu Wei and David Brooks} } @conference {liang2009design, title = {Design and test strategies for microarchitectural post-fabrication tuning}, booktitle = {Computer Design, 2009. ICCD 2009. IEEE International Conference on}, year = {2009}, pages = {84{\textendash}90}, publisher = {IEEE}, organization = {IEEE}, abstract = {Process variations are a major hurdle for continued technology scaling. Both systematic and random variations will affect the critical delay of fabricated chips, causing a wide frequency and power distribution. Tuning techniques adapt the microarchitecture to mitigate the impact of variations at post-fabrication testing time. This paper proposes a new post-fabrication testing framework that accounts for testing costs. This framework uses on-chip canary circuits to capture systematic variation while using statistical analysis to estimate random variation. We derive regression models to predict chip performance and power. These techniques comprise an integrated framework that identifies the most energy efficient post-fabrication tuning configuration for each chip.}, url = {http://dx.doi.org/10.1109/ICCD.2009.5413170}, author = {Xiaoyao Liang and Benjamin Lee and Gu Wei and David Brooks} } @conference {strozek2009efficient, title = {Efficient architectures through application clustering and heterogeneity}, booktitle = {CASES {\textquoteright}06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems}, year = {2009}, pages = {190{\textendash}200}, publisher = {Citeseer}, organization = {Citeseer}, abstract = {

Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This work explores the benefits of architectural customization for a class of embedded architectures typically used in energy-constrained application domains such as sensor node and multimedia processing. We implement a process flow that analyzes runtime profiles of applications and combines this information with a model for our architectural design space providing a robust customization engine built upon a fully automated method for determining an efficient architecture (together with appropriate application transformations). By profiling embedded benchmarks from a variety of sensor and multimedia applications, the paper shows the relative energy savings resulting from various architectural optimizations and identifies the number of architectures that achieves near-optimal savings for a group of applications. This paper proposes the use of heterogeneous chip-multiprocessors as a cost-effective approach to capitalize on the potential energy savings provided by application customization while executing a range of applications efficiently.

}, url = {https://doi.org/10.1145/1176760.1176784}, author = {Lukasz Strozek and David Brooks} } @article {hempstead2009navigo, title = {Navigo: An early-stage model to study power-contrained architectures and specialization}, journal = { Workshop on Modeling, Benchmarking, and Simulation}, year = {2009}, abstract = {As the number of transistors double, it becomes difficult to power all of them within a strict power budget and still achieve the performance gains of that the industry has achieved historically. This work presents, Navigo, a modeling framework for architecture exploration across future process technology generations. The model includes support for voltage and frequency scaling based on ITRS and PTM models. This work is designed to aid architects in the planning stages of next generation microprocessors, by addressing the space between early-stage back-of-the-envelope calculations and later stage cycle accurate simulators. Using parameters from existing commercial processor cores, we show how power consumption limits the theoretical throughput of future processors. Navigo shows that specialization is the answer to circumvent the power density limit that curbs performance gains and resume traditional 1.58x performance growth trends. We present analysis, using next generation of process technologies, that shows the fraction of area that must be allocated for specialization to maintain performance growth must increase with each new generation of process technology.}, author = {Mark Hempstead and Gu Wei and David Brooks} } @conference {lee2008cpr, title = {CPR: Composable performance regression for scalable multiprocessor models}, booktitle = {2008 41st IEEE/ACM International Symposium on Microarchitecture}, year = {2008}, pages = {270{\textendash}281}, publisher = {IEEE}, organization = {IEEE}, abstract = {Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increase the cost of every cycle simulated and shared resource contention that increases the total number of cycles simulated. These effects cause multiprocessor simulation times to scale superlinearly with the number of cores. Composable performance regression (CPR) fundamentally addresses these intractable multiprocessor simulation times, estimating multiprocessor performance with a combination of uniprocessor, contention, and penalty models. The uniprocessor model predicts baseline performance of each core while the contention models predict interfering accesses from other cores. Uniprocessor and contention model outputs are composed by a penalty model to produce the final multiprocessor performance estimate. Trained with a production quality simulator, CPR is accurate with median errors of 6.63, 4.83 percent for dual-, quad-core multiprocessors. Furthermore, composable regression is scalable, requiring 0.33x the simulations required by prior regression strategies.}, url = {https://doi.org/10.1109/MICRO.2008.4771797}, author = {Benjamin Lee and Jamison Collins and Wang, Hong and David Brooks} } @conference {lee2008roughness, title = {Roughness of microarchitectural design topologies and its implications for optimization}, booktitle = {2008 IEEE 14th International Symposium on High Performance Computer Architecture}, year = {2008}, pages = {240{\textendash}251}, publisher = {IEEE}, organization = {IEEE}, abstract = {Recent advances in statistical inference and machine learning close the divide between simulation and classical optimization, thereby enabling more rigorous and robust microarchitectural studies. To most effectively utilize these now computationally tractable techniques, we characterize design topology roughness and leverage this characterization to guide our usage of analysis and optimization methods. In particular, we compute roughness metrics that require high-order derivatives and multi-dimensional integrals of design metrics, such as performance and power. These roughness metrics exhibit noteworthy correlations (1) against regression model error, (2) against non-linearities and non-monotonicities of contour maps, and (3) against the effectiveness of optimization heuristics such as gradient ascent. Thus, this work quantifies the implications of design topology roughness for commonly used methods and practices in microarchitectural analysis.\ }, url = {https://doi.org/10.1109/HPCA.2008.4658643}, author = {Benjamin Lee and David Brooks} } @conference {chung200812, title = {A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13 $μ$m CMOS}, booktitle = {2008 IEEE Custom Integrated Circuits Conference}, year = {2008}, pages = {563{\textendash}566}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper presents a 12.5-Gbps transmitter that uses a lookup table (LUT)-based equalizer to compensate for within-die imperfections. An equalization technique with 2x sampling is proposed to accommodate timing offsets in the multiphase clocks used for 8:1 serialization. LUT code remapping is also demonstrated to compensate for mismatch effects that introduce nonlinearity in the transmit DAC. Experimental results of a 7-bit resolution transmitter with 4-tap equalization, implemented in 0.13 mum CMOS, show the LUT-based equalizer can significantly improve the signal integrity of an otherwise closed eye for data transmitted at 12.5-Gbps.}, url = {https://doi.org/10.1109/CICC.2008.4672147}, author = {Chung Hayun and Liu Andrew and Gu Wei} } @conference {agrawal20088, title = {A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction}, booktitle = {2008 IEEE Custom Integrated Circuits Conference}, year = {2008}, pages = {459{\textendash}462}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40\% and improves receiver timing margins.}, url = {https://doi.org/10.1109/CICC.2008.4672120}, author = {Agrawal, Ankur and Hanumolu, Pavan Kumar and Gu-Yeon Wei} } @article {ratnayake2008high, title = {A high-throughput maximum a posteriori probability detector}, journal = {IEEE Journal of solid-state circuits}, volume = {43}, year = {2008}, pages = {1846{\textendash}1858}, publisher = {IEEE}, abstract = {This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo decoding, can approach performance close to the channel capacity limit. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750MHz while consuming 2.4W. The detector is implemented in a 0.13μm CMOS technology and has a die area of 9.9 mm 2 .}, url = {https://doi.org/10.1109/CICC.2007.4405772}, author = {Ratnayake, Ruwan and Kavcic, Aleksandar and Gu Wei} } @conference {chen2008design, title = {Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies}, booktitle = {Proceedings of the 2008 international symposium on Low Power Electronics \& Design}, year = {2008}, pages = {277{\textendash}282}, abstract = {The need for low-power I/Os is widely recognized, as I/Os take up a significant portion of total chip power. In recent years, researchers have pointed to the potential system-level power savings that can be realized if dynamic voltage scalable I/Os are available. However, substantial challenges remain in building such links. This paper presents the design and implementation details of opto-electronic transceiver front-end blocks where supply voltage can scale from 1.2V to 0.6V with almost linearly scalable bandwidth from 8Gb/s to 4Gb/s, and power consumption from 36mW to 5mW in a 130nm CMOS process. To the best of our knowledge, this is the first circuit demonstration of voltage-scalable optical links. It demonstrates the feasibility of dynamic voltage scalable optical I/Os.}, url = {https://doi.org/10.1145/1393921.1393994}, author = {Chen, Xuning and Gu Wei and Peh Shiuan} } @conference {wei2008instruction, title = {Instruction-driven clock scheduling with glitch mitigation}, booktitle = {Proceeding of the 13th international symposium on Low power electronics and design (ISLPED {\textquoteright}08)}, year = {2008}, pages = {357{\textendash}362}, publisher = {ACM}, organization = {ACM}, abstract = {Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallower pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic power. Experimentally measured results from a 130 nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic power for shallower pipelines. While higher glitch power can severely diminish the power savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover power savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net power savings of 15\% compared to an aggressively clock-gated design.}, url = {https://doi.org/10.1145/1393921.1394017}, author = {Gu Wei and David Brooks and Ali Khan and Xiaoyao Liang} } @conference {liang2008revival, title = {Revival: A variation-tolerant architecture using voltage interpolation and variable latency}, booktitle = {Computer Architecture, 2008. ISCA{\textquoteright}08. 35th International Symposium on}, year = {2008}, pages = {191{\textendash}202}, publisher = {IEEE}, organization = {IEEE}, abstract = {Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip, and among microarchitectural blocks within one core. Hence, it will be difficult to only rely on traditional frequency binning to efficiently cover the large variations that are expected. Furthermore, multiple voltage/frequency domains introduce significant hardware overhead and alone cannot address the full extent of delay variations expected in future multi-core systems. In this paper, we present ReVIVaL, which combines two fine-grained post-fabrication tuning techniques---voltage interpolation(VI) and variable latency(VL). We show that the frequency variation between chips, between cores on one chip, and between functional units within cores can be reduced to a very small range. The effectiveness of these techniques are further verified through experiments on test chips fabricated in a 130 nm CMOS process. Detailed architectural simulations of multi-core processors demonstrate significant performance and power advantages are possible by combining variable latency with voltage interpolation.}, url = {https://doi.org/10.1109/ISCA.2008.27}, author = {Xiaoyao Liang and Gu Wei and David Brooks} } @conference {karpelson2008review, title = {A review of actuation and power electronics options for flapping-wing robotic insects}, booktitle = {2008 IEEE international conference on robotics and automation}, year = {2008}, pages = {779{\textendash}786}, publisher = {IEEE}, organization = {IEEE}, abstract = {Flapping-wing robotic insects require actuators with high power densities at centimeter to micrometer scales. Due to the low weight budget, the selection and design of the actuation mechanism needs to be considered in parallel with the design of the power electronics required to drive it. This paper explores the design space of flapping-wing microrobots weighing 1g and under by determining mechanical requirements for the actuation mechanism, analyzing potential actuation technologies, and discussing the design and realization of the required power electronics. Promising combinations of actuators and power circuits are identified and used to estimate microrobot performance.
\}, url = {https://doi.org/10.1109/ROBOT.2008.4543300}, author = {Karpelson, Michael and Gu Wei and Wood J} } @conference {hempstead2008system, title = {System design considerations for sensor network applications}, booktitle = {2008 IEEE International Symposium on Circuits and Systems (ISCAS)}, year = {2008}, pages = {2566{\textendash}2569}, publisher = {IEEE}, organization = {IEEE}, address = {Seattle, WA}, abstract = {Systems research in the emerging space of wireless sensor networks has exploded. Researchers have deployed nodes composed of a wireless radio, MEMS sensors and low power computation for applications from medical sensing to volcanic monitoring. We must consider several requirements - including the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements - when designing devices for wireless sensor networks. An untethered, fully-integrated node that operates off of energy scavenged from the ambient environment is the ultimate goal. We take an application-driven approach to the design of a wireless sensor network node. Our approach addresses the event-driven nature that is characteristic of many sensor network workloads. We have completed a detailed architectural analysis of this space using a full-system simulator and RTL model. From this analysis, we chose to implement a design that best achieves the power goals and performance requirements of wireless sensor network applications.}, url = {https://doi.org/10.1109/ISCAS.2008.4541980}, author = {Mark Hempstead and Gu Wei and David Brooks} } @article {helal2008highly, title = {A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance}, journal = {IEEE Journal of Solid-State Circuits}, volume = {43}, year = {2008}, pages = {855{\textendash}863}, publisher = {IEEE}, abstract = {This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 mum integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.}, url = {https://doi.org/10.1109/JSSC.2008.917372}, author = {Helal M and Straayer, Z and Gu Wei and Perroth H} } @conference {ildjit, title = {A parallel dynamic compiler for CIL bytecode}, booktitle = {ACM Sigplan Notices}, volume = {43}, year = {2008}, pages = {11-20}, publisher = {ACM}, organization = {ACM}, edition = {4}, abstract = {

Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the potentialities of their hardware parallelism.

At the same time, object code virtualization technologies are achieving a growing popularity, as they allow higher levels of software portability and reuse.

Thus, a virtual execution environment running on a multi-core processor has to run complex, high-level applications and to exploit as much as possible the underlying parallel hardware. We propose an approach that leverages on CMP features to expose a novel pipeline synchronization model for the internal threads of the dynamic compiler.

Thanks to compilation latency masking effect of the pipeline organization, our dynamic compiler, ILDJIT, is able to achieve significant speedups (26\% on average) with respect to the baseline, when the underlying hardware exposes at least two cores.

}, keywords = {helix}, url = {https://doi.org/10.1145/1374752.1374754}, author = {Simone Campanoni and Giovanni Agosta and Stefano Reghizzi} } @article {hempstead2008survey, title = {Survey of hardware systems for wireless sensor networks}, journal = {Journal of Low Power Electronics}, volume = {4}, year = {2008}, pages = {11{\textendash}20}, publisher = {American Scientific Publishers}, abstract = {Wireless sensor networks have been gaining interest as a platform that changes how we interact with the physical world. Applications in medicine, military, inventory management, structural and environmental monitoring, and the like can benefit from low-power wireless nodes that communicate data collected via a variety of sensors. Current deployments of wireless sensor networks (WSN) rely on off-the-shelf commodity-based microcontrollers, but the unoptimized energy consumption of these systems can limit the effective lifetimes. Ideally, researchers would like to deeply embed wireless sensor network nodes in the physical world, relying on energy scavenged from the ambient environment. This paper provides a survey of ultra low power processors specifically designed for WSN applications that have begun to emerge from research labs, which require detailed understanding of tradeoffs between application space, architecture, and circuit techniques to implement these low-power systems.}, url = {http://dx.doi.org/10.1166/jolpe.2008.156}, author = {Mark Hempstead and Michael Lyons and David Brooks and Gu Wei} } @conference {lee2008efficiency, title = {Efficiency trends and limits from comprehensive microarchitectural adaptivity}, booktitle = {ACM SIGARCH Computer Architecture News}, volume = {43}, year = {2008}, pages = {36{\textendash}47}, publisher = {ACM}, organization = {ACM}, edition = {3}, abstract = {

ncreasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B point.

With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips3/w efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements.

}, url = {https://doi.org/10.1145/1353536.1346288}, author = {Benjamin Lee and David Brooks} } @conference {brownell2008evaluation, title = {Evaluation of voltage interpolation to address process variations}, booktitle = {Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design}, year = {2008}, pages = {529{\textendash}536}, publisher = {IEEE Press}, organization = {IEEE Press}, abstract = {

Abstract {\textemdash} Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks and shows that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. The analysis shows that the scheme can match the nominal delay target with a 10 \% power cost, or for the same power budget, incur only a 9 \% delay overhead after variations. I.

}, author = {Kevin Brownell and Gu Wei and David Brooks} } @conference {gupta2008decor, title = {DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors}, booktitle = {2008 IEEE 14th International Symposium on High Performance Computer Architecture}, year = {2008}, pages = {381{\textendash}392}, publisher = {IEEE}, organization = {IEEE}, abstract = {Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to undesired effects, like timing violations, which may result in incorrect execution of applications. Several recent architectural solutions for inductive noise have been proposed that, unfortunately, have a strong correlation to the underlying power-delivery package model and require a feedback loop that is largely constrained by the voltage/current sensor characteristics. The resulting solutions are not robust across a wide range of microprocessor designs and packaging technologies. This paper proposes a Delayed-commit and rollback scheme (DeCoR) that guarantees correctness, insensitive to the package model or the responsiveness of the voltage sensors. In particular, our approach recovers from, rather than attempting to avoid, voltage emergencies. This approach incurs a small performance penalty when compared to an ideal machine that does not have voltage emergencies. We show that explicit checkpoint-recovery schemes, intended to handle infrequent events, e.g., radiation-induced soft errors, suffer from large performance overheads for frequently-occurring voltage emergencies. DeCoR requires very few modifications to modern processor designs, as it leverages the existing store queue and reorder buffers. Unlike conventional designs that conservatively protect all components of the processor from inductive noise with overly-large timing margins, our approach only requires conservative protection of the architected register state and cache write paths.}, url = {https://doi.org/10.1109/HPCA.2008.4658654}, author = {Meeta Gupta and Krishna Rangan and Michael Smith and Gu Wei and David Brooks} } @conference {kim2008system, title = {System level analysis of fast, per-core DVFS using on-chip switching regulators}, booktitle = {2008 IEEE 14th International Symposium on High Performance Computer Architecture}, year = {2008}, pages = {123{\textendash}134}, publisher = {Ieee}, organization = {Ieee}, address = {Salt Lake City, UT, USA}, abstract = {Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.}, url = {https://doi.org/10.1109/HPCA.2008.4658633}, author = {Wonyoung Kim and Meeta Gupta and Gu Wei and David Brooks} } @conference {liang2008process, title = {A process-variation-tolerant floating-point unit with voltage interpolation and variable latency}, booktitle = {2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers}, year = {2008}, pages = {404{\textendash}623}, publisher = {IEEE}, organization = {IEEE}, address = {San Francisco, CA, USA}, abstract = {This paper explores two fine-grained, post-fabrication circuit-tuning techniques to combat process variation for pipelined logic componentsrdquo voltage interpolation and variable latency. These techniques are applied to a single-precision floating-point unit (FPU) designed using a standard CAD synthesis flow in a 0.13 mum CMOS logic process with 8 metal layers. Measured results from fabricated chips show that both techniques provide wide frequency tuning range to deal with frequency fluctuations arising from process variations with minimal power overhead, and in some configurations, power savings.}, url = {https://doi.org/10.1109/ISSCC.2008.4523228}, author = {Xiaoyao Liang and David Brooks and Gu Wei} } @article {hanumolu2008sub, title = {A sub-picosecond resolution 0.5{\textendash}1.5 GHz digital-to-phase converter}, journal = {IEEE Journal of Solid-State Circuits}, volume = {43}, year = {2008}, pages = {414{\textendash}424}, publisher = {IEEE}, abstract = {A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.}, url = {http://dx.doi.org/10.1109/JSSC.2007.914287}, author = {Hanumolu Kumar and Kratyuk Volodymyr and Gu Wei and Moon Un-Ku} } @article {hanumolu2008wide, title = {A wide-tracking range clock and data recovery circuit}, journal = {IEEE Journal of Solid-State Circuits}, volume = {43}, year = {2008}, pages = {425{\textendash}439}, publisher = {IEEE}, abstract = {A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER \<10 -12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.}, url = {https://doi.org/10.1109/JSSC.2007.914290}, author = {Hanumolu Kumar and Gu Wei and Moon Ku} } @article {liang2008replacing, title = {Replacing 6t srams with 3t1d drams in the l1 data cache to combat process variability}, journal = {Micro, IEEE}, volume = {28}, year = {2008}, pages = {60{\textendash}68}, publisher = {IEEE}, abstract = {With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.}, url = {https://doi.org/10.1109/MM.2008.12}, author = {Xiaoyao Liang and Ramon Canal and Gu Wei and David Brooks} } @article {lyons2008application, title = {Application-Specific Hardware Design for Wireless Sensor Network Energy and Delay Reduction}, journal = {Workshop on Optimizations for DSP and Embedded Systems (ODES)}, year = {2008}, publisher = {Citeseer}, abstract = {Battery-powered embedded systems, such as wireless sensor network (WSN) motes, require low energy usage to extend system lifetime. WSN motes must power sensors, a processor, and a radio for wireless communication over long periods of time, and are therefore particularly sensitive to energy use. Recent techniques for reducing WSN energy consumption, such as aggregation, require additional computation to reduce the cost of sending data by minimizing radio data transmissions. Larger demands on the processor will require more computational energy, but traditional energy reduction approaches, such as multi-core scaling with reduced frequency and voltage may prove heavy handed and ineffective for motes. Instead, application-specific hardware design (ASHD) architectures can reduce computational energy consumption by processing operations common to specific applications more efficiently than a general purpose processor. By the nature of their deeply embedded operation, motes support a limited set of applications, and thus the conventional general purpose computing paradigm may not be well-suited to mote operation. Both simple and complex operations can improve performance and use orders of magnitude less energy with application-specific hardware. This paper examines the design considerations of a hardware accelerator for compressed Bloom filters, a data structure for efficiently storing set membership. Additionally, we evaluate our ASHD design for three representative wireless sensor network applications: monitoring network-wide mote status, object tracking, and on-mote duplicate packet filtering. We demonstrate that ASHD design reduces network latency by 59\% and computational energy by 98\%, and show the need for architecting processors for ASHD accelerators.\ }, url = {http://www.eecs.harvard.edu/~mjlyons/papers/lyons-brooks-odes6.pdf}, author = {Michael Lyons and David Brooks} } @article {liang2008design, title = {Design and Test Strategies for Microarchitectural PostFabrication}, year = {2008}, abstract = {

Process variations are a major hurdle for continued technology scaling. Both systematic and random variations will affect the critical delay of fabricated chips, causing a wide frequency and power distribution. Tuning techniques adapt the microarchitecture to mitigate the impact of variations at post-fabrication testing time. This paper proposes a new post-fabrication testing framework that accounts for testing costs. This framework uses on-chip canary circuits to capture systematic variation while using statistical analysis to estimate random variation. We derive regression models to predict chip performance and power. These techniques comprise an integrated framework that identifies the most energy efficient post-fabrication tuning configuration for each chip.

}, url = {https://doi.ieeecomputersociety.org/10.1109/ICCD.2009.5413170}, author = {Xiaoyao Liang and Benjamin Lee and Gu Wei and David Brooks} } @conference {ratnayake2007bit, title = {A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders}, booktitle = {IEEE GLOBECOM 2007-IEEE Global Telecommunications Conference}, year = {2007}, pages = {265{\textendash}270}, publisher = {IEEE}, organization = {IEEE}, abstract = {A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.}, url = {http://dx.doi.org/10.1109/GLOCOM.2007.57}, author = {Ratnayake NS and Haratsch F and Gu Wei} } @conference {liang2007process, title = {Process variation tolerant 3T1D-based cache architectures}, booktitle = {Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture}, year = {2007}, pages = {15{\textendash}26}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, address = {Chicago, IL, USA}, abstract = {Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continued technology scaling. In this paper, we propose new on-chip memory architectures based on novel 3T1D DRAM (3-transistor, 1-diode dynamic memory) cells. We provide a detailed comparison between 6T and 3T1D designs in the context of a L1 data cache. The effects of physical device variation on a 3T1D cache can be lumped into variation of data retention times. This paper proposes a range of cache refresh and placement schemes that are sensitive to retention time, and we show that most of the retention time variations can be masked by the microarchitecture when using these schemes. We have performed detailed circuit and architectural simulations assuming different degrees of variability in advanced technology nodes, and we show that the resulting memory architecture can tolerate large process variations with little or even no impact on performance when compared to ideal 6T SRAM designs. Furthermore, these designs are robust to memory cell stability issues and can achieve large power savings. These advantages make the new memory architectures a promising choice for on-chip variation-tolerant cache structures required for next generation microprocessors.}, url = {https://doi.org/10.1109/MICRO.2007.40}, author = {Xiaoyao Liang and Ramon Canal and Gu Wei and David Brooks} } @conference {liang2007process, title = {Process variation tolerant register files based on dynamic memories}, booktitle = {Workshop on Architectural Support for Gigascale Integration (ASGI-07) in conjunction with ISCA}, year = {2007}, abstract = {Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM (6-transistor static memory) structures and will become critical with continued technology scaling. In this paper, we propose new on-chip memory architectures based on novel 3T1D DRAM (3-transistor, 1-diode dynamic memory) cells. We provide a detailed comparison between 6T and 3T1D designs in the context of a L1 data cache. The effects of physical device variation on a 3T1D cache can be lumped into variation of data retention times. This paper proposes a range of cache refresh and placement schemes that are sensitive to retention time, and we show that most of the retention time variations can be masked by the microarchitecture when using these schemes.Ω}, author = {Xiaoyao Liang and Ramon Canal and Gu Wei and David Brooks} } @article {liang2007processb, title = {Process Variation Tolerant Register Files Based On Dynamic Memories}, journal = {Workshop on Architectural Support for Gigascale Integration, held with Int{\textquoteright}l Symposium on Computer Architecture (ISCA-34)}, year = {2007}, abstract = {Transistor gate length and threshold voltage variability due to process variations will greatly impact the stability, leakage power, and performance of future microprocessors. These variations are especially detrimental to continued scaling of 6T SRAM (6-transistor static memory) structures. This paper proposes replacing traditional SRAM-based cells in mutliported register files with cells based on 3T1D DRAM (3-transistor, 1diode dynamic memory) cells, which can absorb the effects of device physical variations into a single parameter{\textendash} the data retention time. By leveraging the transient data in the processor and dependency slack in the pipeline, retention time variation can be hidden into the existing processor architecture. Thus the proposed register file can effectively tolerate very large process variation with little or even no impact on performance, addresses stability concerns, and reduces power consumption, when compared with ideal SRAM-based designs. Detailed circuit and architectural simulations and analysis verify a 1\% normalized performance loss even under very large process variations, and 22\% average power savings.}, url = {https://www.eecs.harvard.edu/~dbrooks/liang2007-asgi.pdf}, author = {Xiaoyao Liang and Ramon Canal and Gu Wei and David Brooks} } @conference {liang2007architectural, title = {Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques}, booktitle = {Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design}, year = {2007}, pages = {824{\textendash}830}, publisher = {IEEE Press}, organization = {IEEE Press}, abstract = {The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and high-performance microprocessors incorporate large on-chip cache and similar SRAM-based or CAM-based structures, and these components can consume a significant fraction of the total chip power. Thus an accurate power modeling method for such structures is important in early architecture design studies. We present a unified architecture-level power modeling methodology for array structures which is highly-accurate, parameterizable, and technology scalable. We demonstrate the applicability of the model to different memory structures (SRAMs and CAMs) and include leakage-variability in advanced technologies. The power modeling approach is validated against HSPICE power simulation results, and we show power estimation accuracy within 5\% of detailed circuit simulations.}, url = {https://doi.org/10.1109/ICCAD.2007.4397367}, author = {Xiaoyao Liang and Kerem Turgay and David Brooks} } @conference {burnham2007comprehensive, title = {A comprehensive phase-transfer model for delay-locked loops}, booktitle = {2007 IEEE Custom Integrated Circuits Conference}, year = {2007}, pages = {627{\textendash}630}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper presents a comprehensive model for analyzing the behavior of an analog delay-locked loop (DLL). Unlike previous models, the proposed version includes both constant and variable phase-offset terms, making it possible to calculate jitter transfer characteristics, stability, and static phase errors from a single unified model. The topology more closely approximates the underlying architecture of the DLL, resulting in improved accuracy and enabling better tradeoffs between bandwidth, stability, and power.}, url = {https://doi.org/10.1109/CICC.2007.4405810}, author = {Burnham R and Gu Wei and Yang Ken and Hindi Haitham} } @conference {hanumolu2007digitally, title = {Digitally-enhanced phase-locking circuits}, booktitle = {2007 IEEE Custom Integrated Circuits Conference}, year = {2007}, pages = {361{\textendash}368}, publisher = {IEEE}, organization = {IEEE}, abstract = {In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) implemented in deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed in detail. The implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs in digital systems requiring high-performance PLLs.}, url = {https://doi.org/10.1109/CICC.2007.4405753}, author = {Hanumolu Kumar and Gu Wei and Moon Ku and Mayaram, Kartikeya} } @conference {ratnayake2007serial, title = {Serial Sum-Product Architecture for Low-Density Parity-Check Codes}, booktitle = {2007 16th International Conference on Computer Communications and Networks}, year = {2007}, pages = {154{\textendash}158}, publisher = {IEEE}, organization = {IEEE}, abstract = {A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to check node messages sequentially, while the check node computations are broken up into several steps and computed on the fly. This bit node centric architecture requires considerably less memory compared to other serial architectures, including the check node centric architecture.}, url = {http://dx.doi.org/10.1109/ICCCN.2007.4317812}, author = {Ratnayake NS and Haratsch, F and Gu Wei} } @conference {gupta2007towards, title = {Towards a software approach to mitigate voltage emergencies}, booktitle = {Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on}, year = {2007}, pages = {123{\textendash}128}, publisher = {IEEE}, organization = {IEEE}, abstract = {Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. One approach suggested has been to not only react to these fluctuations but also attempt to eliminate future occurrences of these fluctuations by dynamically modifying the executing program. This paper investigates the potential of a very simple dynamic scheme to appreciably reduce the number of run-time voltage emergencies. It shows that we can map many of the voltage emergencies in the execution of the SPEC benchmarks on an aggressive superscalar design to a few static loops, categorize the microarchitectural cause of the emergencies in each important loop through simple observations and a simple priority function, and finally apply straight forward software optimization strategies to mitigate up to 70\% of the future voltage swings.}, url = {https://doi.org/10.1145/1283780.1283808}, author = {Meeta Gupta and Krishna Rangan and Michael Smith and Gu Wei and David Brooks} } @conference {helal2007low, title = {A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation}, booktitle = {2007 IEEE Symposium on VLSI Circuits}, year = {2007}, pages = {166{\textendash}167}, publisher = {IEEE}, organization = {IEEE}, abstract = {This paper presents a 1.6 GHz multiplying delay-locked loop (MDLL) that leverages time-to-digital conversion and a digital correlation technique to achieve low deterministic jitter while still maintaining low random jitter. A proposed time-to-digital converter consists of a ring oscillator that is gated on and off to accurately measure time and scramble the measurement{\textquoteright}s residual error. Using a 50 MHz reference, the prototype system has measured reference spurs less than -59 dBc and an overall measured jitter of 1.41 ps.}, url = {https://doi.org/10.1109/VLSIC.2007.4342700}, author = {Helal M and Straayer Z and Gu Wei and Perrott H} } @article {brooks2007powerb, title = {Power, thermal, and reliability modeling in nanometer-scale microprocessors}, journal = {Micro, IEEE}, volume = {27}, year = {2007}, pages = {49{\textendash}62}, publisher = {IEEE}, abstract = {System integration and performance requirements are dramatically increasing the power consumptions and power densities of high-performance microprocessors. High power consumption introduces challenges to various aspects of microprocessor and computer system design. It increases the cost of cooling and packaging design, reduces system reliability, complicates power supply circuitry design, and reduces battery life. Researchers have recently dedicated intensive effort to power-related design problems. Modeling is the essential first step toward design optimization. In this article, the power, thermal and reliability modeling problems are explained and recent advances in their accurate and efficient analysis are surveyed.}, url = {https://doi.org/10.1109/MM.2007.58}, author = {David Brooks and Robert Dick and Russ Joseph and Li Shang} } @article {lee2007spatial, title = {Spatial Sampling and Regression Strategies}, journal = {Micro, IEEE}, volume = {27}, year = {2007}, pages = {74{\textendash}93}, publisher = {IEEE}, abstract = {This new simulation paradigm for microarchitectural design evaluation and optimization counters growing simulation costs stemming from the exponentially increasing size of design spaces. the authors demonstrate how to obtain a more comprehensive understanding of the design space by selectively simulating a modest number of designs from that space and then more effectively leveraging the simulation data using techniques in statistical inference.}, url = {https://doi.org/10.1109/MM.2007.61}, author = {Benjamin Lee and David Brooks} } @conference {gupta2007understanding, title = {Understanding voltage variations in chip multiprocessors using a distributed power-delivery network}, booktitle = {Design, Automation \&amp; Test in Europe Conference \&amp; Exhibition, 2007. DATE{\textquoteright}07}, year = {2007}, pages = {1{\textendash}6}, publisher = {IEEE}, organization = {IEEE}, address = {Nice, France}, abstract = {Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply current, can be attributed to architectural gating events that reduce power dissipation. In order to study this problem, the authors propose a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, the authors analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. They find that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise, and they describe potentially problematic activity sequences that are unique to CMP architectures}, url = {https://doi.org/10.1109/DATE.2007.364663}, author = {Meeta Gupta and Jarod Oatley and Russ Joseph and Gu Wei and David Brooks} } @conference {lee2007methods, title = {Methods of inference and learning for performance modeling of parallel applications}, booktitle = {Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming}, year = {2007}, pages = {249{\textendash}258}, publisher = {ACM}, organization = {ACM}, abstract = {

Increasing system and algorithmic complexity combined with a growing number of tunable application parameters pose significant challenges for analytical performance modeling. We propose a series of robust techniques to address these challenges. In particular, we apply statistical techniques such as clustering, association, and correlation analysis, to understand the application parameter space better. We construct and compare two classes of effective predictive models: piecewise polynomial regression and artifical neural networks. We compare these techniques with theoretical analyses and experimental results. Overall, both regression and neural networks are accurate with median error rates ranging from 2.2 to 10.5 percent. The comparable accuracy of these models suggest differentiating features will arise from ease of use, transparency, and computational efficiency.

}, url = {https://doi.org/10.1145/1229428.1229479}, author = {Benjamin Lee and David Brooks and Bronis Supinski and Martin Schulz and Karan Singh and Sally McKee} } @conference {lee2007illustrative, title = {Illustrative design space studies with microarchitectural regression models}, booktitle = {High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on}, year = {2007}, pages = {340{\textendash}351}, publisher = {IEEE}, organization = {IEEE}, address = {Phoenix, Arizona, USA}, abstract = {We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to identify trends from a sparse simulation of the space. The computational efficiency of sampling and inference enables new capabilities in design space exploration. We illustrate these capabilities using performance and power models for three studies of a 260,000 point design space: (1) Pareto frontier analysis, (2) pipeline depth analysis, and (3) multiprocessor heterogeneity analysis. For each study, we provide an assessment of predictive error and sensitivity of observed trends to such error. We construct Pareto frontiers and find predictions for Pareto optima are no less accurate than those for the broader design space. We reproduce and enhance prior pipeline depth studies, demonstrating constrained sensitivity studies may not generalize when many other design parameters are held at constant values. Lastly, we identify efficient heterogeneous core designs by clustering per benchmark optimal architectures. Collectively, these studies motivate the application of techniques in statistical inference for more effective use of modern simulator infrastructure}, url = {https://doi.org/10.1109/HPCA.2007.346211}, author = {Benjamin Lee and David Brooks} } @article {kim2007enabling, title = {Enabling on-chip switching regulators for multi-core processors using current staggering}, journal = {Proceedings of the Work. on Architectural Support for Gigascale Integration}, year = {2007}, publisher = {Citeseer}, abstract = {

Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a wellknown technique to reduce energy in portable systems, but DVFS effectiveness suffers from the fact that voltage transitions occur on the order of tens of microseconds. Voltage regulators that are integrated on the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and improved power delivery. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics. In this paper, we discuss architectural support for on-chip regulator designs. Specifically, we show that in a chip-multiprocessor system, current staggering can be employed by restricting the simultaneous enabling/disabling of cores due to clock gating. We discuss tradeoffs between current staggering and regulator circuit design parameters, and we show that regulation efficiency of greater than 80\% is possible for a variety of multi-threaded applications.

}, author = {Wonyoung Kim and Meeta Gupta and Gu-Wei and David Brooks} } @article {lee2007statistical, title = {Statistical inference for efficient microarchitectural analysis}, journal = {SC {\textquoteright}06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing}, year = {2007}, pages = {130{\textendash}es}, abstract = {

Microarchitectural design exploration is often inefficient and ad hoc due to computational costs of simulators. Trends toward multi-core, multi-threading lead to diversity in viable core designs, thereby requiring comprehensive design exploration while exponentially increasing design space size. Similarly, application performance topology is a function of input parameters, but models to optimize performance and/or predict scalability are increasingly difficult to derive analytically due to system complexity. We collect measurements sampled sparsely, uniformly at random from the space of interest and formulate non-linear regression models. We demonstrate the broad effectiveness of regression for predicting (1) the power and performance of a microarchitectural design space with median error rates of 5.5 to 7.5 percent using 1K samples from a 1B point space and (2) the performance of parallel applications, Semicoarsening Multigrid and High-Performance Linpack, with median error rates of 2.5 to 5.0 percent using 500 samples from more than 3K points.

}, url = {https://doi.org/10.1145/1188455.1188591}, author = {Benjamin Lee and David Brooks} } @journal {hempstead2007ultra, title = {Ultra low power system for sensor network applications}, year = {2007}, note = {US Patent App. 11/685,721}, abstract = {Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networks have several important attributes that require special attention to device design. These include the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements. Ultimately, the "holy grail" of this design space is a truly untethered device that operates off of energy scavenged from the ambient environment. In this paper, we describe an application-driven approach to the architectural design and implementation of a wireless sensor device that recognizes the event-driven nature of many sensor-network workloads. We have developed a full-system simulator for our sensor node design to verify and explore our architecture. Our simulation results suggest one to two orders of magnitude reduction in power dissipation over existing commodity-based systems for an important class of sensor network applications. We are currently in the implementation stage of design, and plan to tape out the first version of our system within the next year.}, url = {https://doi.org/10.1109/ISCA.2005.12}, author = {Mark Hempstead and Nikhil Tripathi and Patrick Mauro and Gu Wei and David Brooks} } @article {li2006impact, title = {Impact of thermal constraints on multi-core architectures}, journal = {10th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems, San Diego}, year = {2006}, abstract = {This paper shows how thermal constraints affect the multidimensional design space for chip multiprocessors, considering the inter-related variables of CPU count, pipeline depth, superscalar width, L2 cache size, and operating voltage and frequency. The results show the importance of thermal modeling and the need for new thermal modeling capabilities and hence the need for collaboration between the thermal engineeringand computerarchitecturecommunities. Thermalconstraints both shift the optimal intra- and inter-core organization, and dominate other physical constraints such as pinbandwidth and power delivery. Different thermal constraints also require different optimization strategies. For aggressive cooling solutions, reducing power density is at least as important as reducing total power, while for low-cost cooling solutions, reducing total power is more important.}, url = {https://doi.org/10.1109/ITHERM.2006.1645333}, author = {Yingmin Li and Benjamin Lee and David Brooks and Zhigang Hu and Kevin Skadron} } @conference {fang2006system, title = {System-on-chip architecture design for intelligent sensor networks}, booktitle = {2006 International Conference on Intelligent Information Hiding and Multimedia}, year = {2006}, pages = {579{\textendash}582}, publisher = {IEEE}, organization = {IEEE}, abstract = {While wireless sensor networks can generically be used for a wide variety of applications, breakthrough innovations are most often achieved when driven by a genuine need or application, with its specific system-level and science-related requirements and objectives. Hence, our work focuses on the development of wireless sensor network system-on-chip devices and supporting software for volcano monitoring, which we call Sensor Network for Active Volcanoes (SNAV). In this paper we present preliminary results of our research and development work on intelligent sensor networks for monitoring hazardous environments especially the SNAV system-on-chip design for active volcanoes monitoring.}, url = {https://doi.org/10.1109/IIH-MSP.2006.265069}, author = {Fang Chi and Kedar, Sharon and Owen, Susan and Gu Wei and David Brooks and Lees, Jonathan} } @conference {liang2006mitigating, title = {Mitigating the impact of process variations on processor register files and execution units}, booktitle = {Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on}, year = {2006}, pages = {504{\textendash}514}, publisher = {IEEE}, organization = {IEEE}, abstract = {Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. One serious manifestation of this increased variability is a reduction in the mean frequency of fabricated chips due to fluctuations in device characteristics causing reduced circuit performance. In this paper, we propose to mitigate the impact of variations through variable-latency register files and execution units which are key architectural components that may encounter variability problems. We also illustrate the importance of closing the gap in expected delay of these distinct structures. A post fabrication test and configuration strategy is proposed. We find that 23\% mean frequency improvement with an average IPC loss of 3\% (and never exceeding 5\% for worst case chips) is possible for the 65nm technology node by properly adopting the proposed schemes}, url = {https://doi.org/10.1109/MICRO.2006.37}, author = {Xiaoyao Liang and David Brooks} } @conference {lee2006accurate, title = {Accurate and efficient regression modeling for microarchitectural performance and power prediction}, booktitle = {ACM SIGOPS Operating Systems Review}, volume = {40}, year = {2006}, pages = {185{\textendash}194}, publisher = {ACM}, organization = {ACM}, edition = {5}, abstract = {

We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a large microarchitectural design space. This paper addresses fundamental challenges in microarchitectural simulation cost by reducing the number of required simulations and using simulated results more effectively via statistical modeling and inference.Specifically, we derive and validate regression models for performance and power. Such models enable computationally efficient statistical inference, requiring the simulation of only 1 in 5 million points of a joint microarchitecture-application design space while achieving median error rates as low as 4.1 percent for performance and 4.3 percent for power. Although both models achieve similar accuracy, the sources of accuracy are strikingly different. We present optimizations for a baseline regression model to obtain (1) application-specific models to maximize accuracy in performance prediction and (2) regional power models leveraging only the most relevant samples from the microarchitectural design space to maximize accuracy in power prediction. Assessing sensitivity to the number of samples simulated for model formulation, we find fewer than 4,000 samples from a design space of approximately 22 billion points are sufficient. Collectively, our results suggest significant potential in accurate and efficient statistical inference for microarchitectural design space exploration via regression models.

}, url = {https://doi.org/10.1145/1168917.1168881}, author = {Benjamin Lee and David Brooks} } @conference {liang2006microarchitecture, title = {Microarchitecture parameter selection to optimize system performance under process variation}, booktitle = {Computer-Aided Design, 2006. ICCAD{\textquoteright}06. IEEE/ACM International Conference on}, year = {2006}, pages = {429{\textendash}436}, publisher = {IEEE}, organization = {IEEE}, abstract = {

Design variability due to within-die and die-to-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. This variability manifests itself by increasing the number and criticality of long delay paths. To quantify this impact, we use an architectural process variation model that is appropriate for the analysis of system performance in the early-stages of the design process. We propose a method of selecting microarchitectural parameters to mitigate the frequency impact due to process variability for distinct structures, while minimizing IPC (instructions-per-cycle) loss. We propose an optimization procedure to be used for system-level design decisions, and we find that joint architecture and statistical timing analysis can be more advantageous than pure circuit level optimization. Overall, the technique can improve the 90\% yield frequency by about 14\% with 3\% IPC loss for a baseline machine with a 20FO4 logic depth per pipestage. This approach is sensitive to the selection of processor pipeline depth, and we demonstrate that machines with aggressive pipelines will experience greater challenges in coping with process variability.

}, url = {https://doi.org/10.1109/ICCAD.2006.320152}, author = {Xiaoyao Liang and David Brooks} } @conference {strozek2006efficient, title = {Efficient architectures through application clustering and architectural heterogeneity}, booktitle = {Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems}, year = {2006}, pages = {190{\textendash}200}, publisher = {ACM}, organization = {ACM}, abstract = {

Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This work explores the benefits of architectural customization for a class of embedded architectures typically used in energy-constrained application domains such as sensor node and multimedia processing. We implement a process flow that analyzes runtime profiles of applications and combines this information with a model for our architectural design space providing a robust customization engine built upon a fully automated method for determining an efficient architecture (together with appropriate application transformations). By profiling embedded benchmarks from a variety of sensor and multimedia applications, the paper shows the relative energy savings resulting from various architectural optimizations and identifies the number of architectures that achieves near-optimal savings for a group of applications. This paper proposes the use of heterogeneous chip-multiprocessors as a cost-effective approach to capitalize on the potential energy savings provided by application customization while executing a range of applications efficiently.

}, url = {https://doi.org/10.1145/1176760.1176784}, author = {Lukasz Strozek and David Brooks} } @article {lee2006wild, title = {Wild and Crazy Ideas Session-Session 5-Estimation and Prediction of Power and Performance-Accurate and Efficient Regression Modeling for Microarchitectural Performance and Power Prediction}, journal = {SIGOPS Operating Systems Review}, volume = {40}, year = {2006}, pages = {185{\textendash}194}, publisher = {[New York, NY, ACM Special Interest Group on Operating Systems]}, abstract = {

We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a large microarchitectural design space. This paper addresses fundamental challenges in microarchitectural simulation cost by reducing the number of required simulations and using simulated results more effectively via statistical modeling and inference.Specifically, we derive and validate regression models for performance and power. Such models enable computationally efficient statistical inference, requiring the simulation of only 1 in 5 million points of a joint microarchitecture-application design space while achieving median error rates as low as 4.1 percent for performance and 4.3 percent for power. Although both models achieve similar accuracy, the sources of accuracy are strikingly different. We present optimizations for a baseline regression model to obtain (1) application-specific models to maximize accuracy in performance prediction and (2) regional power models leveraging only the most relevant samples from the microarchitectural design space to maximize accuracy in power prediction. Assessing sensitivity to the number of samples simulated for model formulation, we find fewer than 4,000 samples from a design space of approximately 22 billion points are sufficient. Collectively, our results suggest significant potential in accurate and efficient statistical inference for microarchitectural design space exploration via regression models.

}, url = {https://doi.org/10.1145/1168857.1168881}, author = {BC Lee and David Brooks} } @conference {hempstead2006architecture, title = {Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations}, booktitle = {Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems}, year = {2006}, pages = {368{\textendash}378}, publisher = {ACM}, organization = {ACM}, abstract = {

Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for low-throughput, energy-constrained applications. Unlike traditional performance oriented applications, sensor network nodes are primarily constrained by operation lifetime, which is limited by power consumption. Advanced CMOS process technologies provide ever increasing transistor density and improved performance characteristics. However, shrinking feature size and decreasing threshold voltages also lead to significant increases in leakage current, which is especially troublesome for applications with significant idle times. This work investigates tradeoffs between leakage and active power for low-throughput applications. We study these issues across a range of process technologies on a computing architecture that provides explicit support for fine-grain leakage-control techniques such as Vdd-gating and adaptive body bias. We present a methodology for selecting design parameters, including choice of process technology, that makes the optimal tradeoff between active power and leakage power for a given workload. Our results show that leakage power will dominate the selection of process technology, and architectures that support advanced leakage control techniques at the circuit level will be essential. We argue that without advanced low-power architectures future nano-scale process technologies will not be suited for sensor network applications.

}, url = {https://doi.org/10.1145/1176760.1176805}, author = {Mark Hempstead and Gu Wei and David Brooks} } @article {lee2006regressionb, title = {Regression Modeling Strategies for Parameter Space Exploration}, year = {2006}, abstract = {Increasing system and algorithmic complexity, combined with a growing number of tuanble application parameters, pose significant challenges for analytical performance modeling. This report outlines a series of robust techniques that enable efficient parameter space exploration based on empirical statistical modeling. In particular, this report applies statistical techniques such as clustering, association, correlation analyses to understand the parameter space better. Results from these statistical techniques guide the construction of piecewise polynomial regression models. Residual and significance tests ensure the resulting model is unbiased and efficient We demonstrate these techniques in R, a statistical computing environment, for predicting the performance of semicoarsening multigrid. 50 and 75 percent of predictions achieve error rates of 5.5 and 10.0 percent or less, respectively.}, author = {Benjamin Lee and David Brooks and Bronis Supinski and Martin Schulz} } @conference {hanumolu20061, title = {A 1.6 Gbps digital clock and data recovery circuit}, booktitle = {IEEE Custom Integrated Circuits Conference 2006}, year = {2006}, pages = {603{\textendash}606}, publisher = {IEEE}, organization = {IEEE}, abstract = {A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop filter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13mum CMOS process achieves BER \< 10 -12 , plusmn1500ppm lock-in range, plusmn2500ppm tracking range, recovered clock jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps}, url = {10.1109/CICC.2006.320829}, author = {Hanumolu Kumar and Kim, Gyu and Gu Wei and Moon Ku} } @conference {tan2006adaptive, title = {Adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator for optimal jitter performance}, booktitle = {IEEE Custom Integrated Circuits Conference 2006}, year = {2006}, pages = {749{\textendash}752}, publisher = {IEEE}, organization = {IEEE}, address = {San Jose, CA, USA}, abstract = {This paper presents an adaptive-bandwidth mixing PLL/DLL (MX-PDLL) based multi-phase clock generator that can operate as a PLL, DLL, or a mixture of the two. Moreover, this clock generator can be used in a proposed dual-loop CDR to minimize output clock jitter under various noise environments. A test-chip prototype of the MX-PDLL and a 360deg phase rotator was fabricated in a 0.18mum CMOS process, operating off of a 1.8V supply. Experimentally measured results verify that while PLL-mode operation offers the ability to better filter quantization noise from the digital CDR control, shifting towards DLL-mode operation offers the ability to reduce jitter as the amount of on-chip noise increases}, url = {https://doi.org/10.1109/CICC.2006.320967}, author = {TanYuan and Gu Wei} } @conference {tan2006phase, title = {Phase mismatch detection and compensation for PLL/DLL based multi-phase clock generator}, booktitle = {IEEE Custom Integrated Circuits Conference 2006}, year = {2006}, pages = {417{\textendash}420}, publisher = {IEEE}, organization = {IEEE}, address = {San Jose, CA, USA}, abstract = {Device mismatch and systematic imbalances in the physical design can cause static phase mismatch in a PLL/DLL based multi-phase clock generator and degrade performance. This problem gets worse in deep sub-micron technologies. Interleaved transceiver architectures require precise clocking to maximize data rate and minimize bit errors. In this paper, a static phase mismatch compensation scheme for multiple sampling clocks is proposed and tested in an adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator. The proposed charge pump compensator and power efficient phase-averaging network together reduce the static phase mismatch standard deviation by 37\% when operating in DLL mode. A simple and robust duty-cycle correction circuit exhibits a small residual error of 0.65\% across a wide range (36\% to 49\%) of input clock duty-cycle values}, url = {https://doi.org/10.1109/CICC.2006.320986}, author = {TanYuan and Gu Wei} } @conference {howard2006pulsenet, title = {Pulsenet-A Parallel Flash Sampler and Digital Processor IC for Optical SETI}, booktitle = {IEEE Custom Integrated Circuits Conference 2006}, year = {2006}, pages = {261{\textendash}264}, publisher = {IEEE}, organization = {IEEE}, abstract = {

PulseNet is a full-custom IC with parallel flash ADC and digital processing that enables an all-sky optical search for extraterrestrial intelligence. It integrates 448 sense amplifiers that digitize 32 analog signals at 1GS/s, and other circuits that filter samples, store candidate signals, and perform astronomical observations. Its ~250,000 CMOS transistors (TSMC 0.25μm) dissipate 1.1W at 400MHz and 2.5V.

}, url = {https://doi.org/10.1109/CICC.2006.320854}, author = {Howard W and Gu Wei and Dally J and Horowitz Paul} } @article {lee2006statistically, title = {Statistically rigorous regression modeling for the microprocessor design space}, journal = {ISCA-33: Workshop on Modeling, Benchmarking, and Simulation}, year = {2006}, abstract = {Regression models enhance existing techniques in detailed microarchitectural simulation by reducing the number of required simulations and using simulation data more efficiently to identify trends and trade-offs. We present a rigorous derivation of such models for microprocessor performanceandpowerprediction, emphasizing the need to apply domain-specific knowledge when performing statistical inference. In particular, we propose sampling observations uniformly at random from a large design space, discuss approaches for identifying statistically significant predictors, and detail strategies for effectively modeling predictor interaction and non-linearity. The resulting models enable computationally efficient statistical inference, requiring the simulation of only 1 in every 5 million points of a joint microarchitecture-application design space while achieving median prediction error rates as low as 4.1 percent for performance and 4.3 percent for power.}, author = {B Lee and David Brooks} } @conference {hanumolu2006wide, title = {A wide tracking range 0.2-4Gbps clock and data recovery circuit}, booktitle = {2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.}, year = {2006}, pages = {71{\textendash}72}, publisher = {IEEE}, organization = {IEEE}, abstract = {

A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18mum CMOS process achieves BER \< 10\ -12\ and consumes 14mW power while operating at 2Gbps. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking

}, url = {https://doi.org/10.1109/VLSIC.2006.1705317}, author = {Hanumolu P and Wei Y and Moon, U-K} } @conference {li2006cmp, title = {CMP design space exploration subject to physical constraints}, booktitle = {High-Performance Computer Architecture, 2006. The Twelfth International Symposium on}, year = {2006}, pages = {17{\textendash}28}, publisher = {IEEE}, organization = {IEEE}, address = {Austin, TX, USA}, abstract = {This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache size, and operating voltage and frequency, under various area and thermal constraints. The results show the importance of joint optimization. Thermal constraints dominate other physical constraints such as pin-bandwidth and power delivery, demonstrating the importance of considering thermal constraints while optimizing these other parameters. For aggressive cooling solutions, reducing power density is at least as important as reducing total power, while for low-cost cooling solutions, reducing total power is more important. Finally, the paper shows the challenges of accommodating both CPU-bound and memory-bound workloads on the same design. Their respective preferences for more cores and larger caches lead to increasingly irreconcilable configurations as area and other constraints are relaxed; rather than accommodating a happy medium, the extra resources simply encourage more extreme optimization points.}, url = {https://doi.org/10.1109/HPCA.2006.1598109}, author = {Yingmin Li and Benjamin Lee and David Brooks and Zhigang Hu and Kevin Skadron} } @article {wu2006dynamic, title = {Dynamic-compiler-driven control for microprocessor energy and performance}, journal = {Micro, IEEE}, volume = {26}, year = {2006}, pages = {119{\textendash}129}, publisher = {IEEE}, abstract = {A general dynamic-compilation environment offers power and performance control opportunities for microprocessors. The authors propose a dynamic-compiler-driven runtime voltage and frequency optimizer. A prototype of their design, implemented and deployed in a real system, achieves energy savings of up to 70 percent}, url = {https://doi.org/10.1109/MM.2006.9}, author = {Qiang Wu and Margaret Martonosi and Douglas Clark and Vijay Reddi and Dan Connors and Youfeng Wu and Jin Lee and David Brooks} } @article {liang2006latency, title = {Latency adaptation for multiported register files to mitigate the impact of process variations}, journal = {Workshop on Architectural Support for Gigascale Integration (ASGI-06, held in conjuction with ISCA-33)}, year = {2006}, abstract = {

Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. This variability manifests itself by increasing the frequency variance and decreasing the mean frequency of fabricated chips. In this paper we develop a model for the impact of variability on the performance of multiported SRAM-based structures such as physical register files which are key architectural components that may encounter variability problems. We find that naively resizing or increasing the access latency of these performance critical datapath resources can have frequency benefits, but may incur a significant IPC loss that limits overall system performance. We propose an extension to latency adaptation called port switching which more efficiently exploits the technique to remedy the IPC loss. We find that even under a conservative, worst case study, 18 \% mean frequency improvement with less than 5 \% IPC loss is possible for the 65nm technology node. Finally, we contrast the impact of die-to-die and within-die variations on chip performance and demonstrate that the proposed technique can compensate the frequency loss mainly due to within-die variations.

}, author = {Xiaoyao Liang and David Brooks} } @booklet {li2006quantifying, title = {Quantifying Latency and Throughput Compromises in CMP Design}, year = {2006}, publisher = {Citeseer}, abstract = {

Designers of chip multiprocessors will increasingly be called upon to optimize for a combination of design metrics under a variety of design constraints. The adoption of chip multiprocessors has also led to a shift in design metrics toward aggregate throughput and away from single thread latency. We examine the compromises between latency and throughput under various power, thermal, area, and bandwidth constraints to quantify the latency penalties of a purely throughput optimized design. We consider a large chip multiprocessor design space that includes core count, core complexity (pipeline dimensions, in-order versus out-of-order execution), and cache hierarchy sizes. We demonstrate an approach to effectively assess trade-offs given a comprehensive core model, a set of optimization criteria, and a set of design constraints. We perform a number of case studies to evaluate these trade-offs, exposing significant single thread latency penalties when optimizing solely for throughput and neglecting other measures of performance. As single thread latency continues to be one of several design metrics, any choice to compromise latency should be well understood before implementation. Collectively, our results suggest single thread latency is still a design metric of importance given that optimizing throughput alone will significantly compromise latency. Furthermore, the case for simple, in-order cores should be taken with caution given this balanced view of performance.

}, url = {https://doi.org/10.18130/V31J2W}, author = {Yingmin Li and Kevin Skadron and Benjamin Lee and David Brooks} } @article {lee2006regression, title = {Regression modeling strategies for microarchitectural performance and power prediction}, journal = {Proceedings of the 2006 ASPLOS Conference}, year = {2006}, pages = {185{\textendash}194}, abstract = {

We propose regression modeling as an effective approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a large microarchitectural design space. This report addresses fundamental challenges in microarchitectural simulation costs via statistical modeling. Specifically, we derive and validate regression models for performance and power. Such models enable computationally efficient statistical inference, requiring the simulation of only 1 in 5 million points of a joint microarchitecture-application design space while achieving error rates as low as 4.1 percent for performance and 4.3 percent for power. Although both models achieve similar accuracy, the sources of accuracy are strikingly different. We present optimizations for a baseline regression model to obtain (1) per benchmark application-specific models designed to maximize accuracy in performance prediction and (2) regional power models leveraging only the most relevant samples from the microarchitectural design space to maximize accuracy in power prediction. Assessing model sensitivity to sample and region sizes, we find 4,000 samples from a design space of approximately 22 billion points, are sufficient for both application-specific and regional modeling and prediction. Collectively, our results suggest significant potential in accurate and efficient statistical inference for microarchitectural design space exploration via regression models.

}, author = {Benjamin Lee and David Brooks} } @article {lee2006statistical, title = {Statistical inference}, year = {2006}, publisher = {Citeseer}, author = {Benjamin Lee and David Brooks} } @conference {wu2005dynamic, title = {A dynamic compilation framework for controlling microprocessor energy and performance}, booktitle = {Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture}, year = {2005}, pages = {271{\textendash}282}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, address = {Barcelona}, abstract = {Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70\% (with 0.5\% performance loss). In addition, SPEC2K INT show up to 44\% energy savings (with 5\% performance loss), SPEC95 FP save up to 64\% (with 4.9\% performance loss), and Olden save up to 61\% (with 4.5\% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22\% vs. 9\%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control}, url = {https://doi.org/10.1109/MICRO.2005.7}, author = {Qiang Wu and Margaret Martonosi and Douglas Clark and Vijay Reddi and Dan Connors and Youfeng Wu and Jin Lee and David Brooks} } @conference {li2005power, title = {Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices}, booktitle = {Proceedings of the 2005 international symposium on Low power electronics and design}, year = {2005}, pages = {173{\textendash}178}, publisher = {ACM}, organization = {ACM}, abstract = {

This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of power dissipation, and both design styles and various clock gating schemes can be found in modern, high-performance processors. Although some work in the circuits domain has explored these issues from a power perspective, thermal treatments are less common, and we are not aware of any work in the architecture domain.We study both SRAM and latch and multiplexer ("latch-mux") designs and their associated clock-gating options. Using circuit-level simulations of both design styles, we derive power-dissipation ratios which are then used in cycle-level power/performance/thermal simulations. We find that even though the "unconstrained" power of SRAM designs is always better than latch-mux designs, latch-mux designs dissipate less power in practice when a structure{\textquoteright}s average occupancy is low but access rate is high, especially when "stall gating" is used to minimize switching power. We also find that latch-mux designs with stall gating are especially promising from a thermal perspective, because they exhibit lower power density than SRAM designs. Overall, when combined with implementation and verification challenges for SRAMs, latch-mux designs with stall gating appear especially promising for designs with thermal constraints. This paper also shows the importance of considering the interaction between architectural and circuit-design choices when performing early-stage design exploration

}, url = {https://doi.org/10.1145/1077603.1077647}, author = {Yingmin Li and Mark Hempstead and Patrick Mauro and David Brooks and Zhigang Hu and Kevin Skadron} } @conference {hempstead2005ultra, title = {An ultra low power system architecture for sensor network applications}, booktitle = {ACM SIGARCH Computer Architecture News}, volume = {33}, year = {2005}, pages = {208{\textendash}219}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, address = {Madison, WI, USA}, abstract = {Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networks have several important attributes that require special attention to device design. These include the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements. Ultimately, the "holy grail" of this design space is a truly untethered device that operates off of energy scavenged from the ambient environment. In this paper, we describe an application-driven approach to the architectural design and implementation of a wireless sensor device that recognizes the event-driven nature of many sensor-network workloads. We have developed a full-system simulator for our sensor node design to verify and explore our architecture. Our simulation results suggest one to two orders of magnitude reduction in power dissipation over existing commodity-based systems for an important class of sensor network applications. We are currently in the implementation stage of design, and plan to tape out the first version of our system within the next year.}, url = {https://doi.org/10.1109/ISCA.2005.12}, author = {Mark Hempstead and Nikhil Tripathi and Patrick Mauro and Gu Wei and David Brooks} } @article {hanumolu2005equalizers, title = {Equalizers for high-speed serial links}, journal = {International journal of high speed electronics and systems}, volume = {15}, year = {2005}, pages = {429{\textendash}458}, publisher = {World Scientific}, abstract = {

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.

}, url = {https://doi.org/10.1142/S0129156405003259}, author = {Hanumolu Kumar and Gu Wei and Moon Ku} } @conference {chen2005exploring, title = {Exploring the design space of power-aware opto-electronic networked systems}, booktitle = {11th International Symposium on High-Performance Computer Architecture}, year = {2005}, pages = {120{\textendash}131}, publisher = {IEEE}, organization = {IEEE}, address = {San Francisco, CA, USA}, abstract = {As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increasing, optical links are replacing electrical links in inter-chassis and inter-board environments. As a result, the power dissipation of optical links is becoming as critical as their speed. In this paper, we first explore options for building high speed optoelectronic links and discuss the power characteristics of different link components. Then, we propose circuit and network mechanisms that can realize power-aware optical links -links whose power consumption can be tuned dynamically in response to changes in network traffic. Finally, we incorporate power control policies along with the power characterization of link circuitry into a detailed network simulator to evaluate the performance cost and power savings of building power aware optoelectronic networked systems. Simulation results show that more than 75\% savings in power consumption can be achieved with the proposed power aware optoelectronic network.}, url = {https://doi.org/10.1109/HPCA.2005.15}, author = {Chen, Xuning and Peh,Shiuan and Gu Wei and Huang, Kai and Prucnal, Paul} } @conference {li2005performance, title = {Performance, energy, and thermal considerations for SMT and CMP architectures}, booktitle = {High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on}, year = {2005}, pages = {71{\textendash}82}, publisher = {IEEE}, organization = {IEEE}, abstract = {Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are still poorly understood. This paper uses Turandot, PowerTimer, and HotSpot to explore this design space for a POWER4/POWER5-like core. For an equal-area comparison with this style of core, we find CMP to be superior in terms of performance and energy-efficiency for CPU-bound benchmarks, but SMT to be superior for memory-bound benchmarks due to a larger L2 cache. Although both exhibit similar peak operating temperatures and thermal management overheads, the mechanism by which SMT and CMP heat up are quite different. More specifically, SMT heating is primarily caused by localized heating in certain key structures, CMP heating is mainly caused by the global impact of increased energy output. Because of this difference in heat up mechanism, we found that the best thermal management technique is also different for SMT and CMP Indeed, non-DVS localized thermal-management can outperform DVS for SMT. Finally, we show that CMP and SMT scales differently as the contribution of leakage power grows, with CMP suffering from higher leakage due to the second core{\textquoteright}s higher temperature and the exponential temperature-dependence of subthreshold leakage.}, url = {https://doi.org/10.1109/HPCA.2005.25}, author = {Yingmin Li and K Skadron and David Brooks and Zhigang Hu} } @article {lee2005effects, title = {Effects of pipeline complexity on SMT/CMP power-performance efficiency}, journal = {Power}, volume = {106}, year = {2005}, pages = {1}, publisher = {Citeseer}, abstract = {We consider processor core complexity and its impli-cations for the power-performance efficiency of SMT and CMP architectures, exploring fundamental trade-offs be-tween the efficiency of multi-core architectures and the com-plexity of their cores from a power-performance perspec-tive. Taking pipeline depth and width as proxies for core complexity, we conduct power-performance simulations of several SMT and CMP architectures employing cores of varying complexity. Our analyses identify efficient pipeline dimensions and outline the implications of using a power-performance efficiency metric for core complexity. Collectively, our results suggest SMT architectures en-able efficient increases in pipeline dimensions and core complexity. Furthermore, reducing pipeline di-mensions in CMP cores is inefficient, assuming ideal power-performance scaling from voltage/frequency scal-ing and circuit re-tuning. Given these conclusions, we formulate guidelines for complexity effective design.}, author = {Benjamin Lee and David Brooks} } @article {srinivasan2005case, title = {The case for microarchitectural awareness of lifetime reliability}, journal = {IEEE Micro}, volume = {25}, year = {2005}, pages = {70{\textendash}80}, author = {Jayanth Srinivasan and Sarita Adve and Pradip Bose and Jude Rivers and Li, Y. and David Brooks and Z Hu and K Skadron and V Srinivasan and M Gschwind} } @article {liang2005highly, title = {Highly accurate power modeling method for SRAM structures with simple circuit simulation}, journal = {2nd Watson Conf. Interaction Between Architecture, Circuits, Compilers}, year = {2005}, author = {Xiaoyao Liang and David Brooks} } @conference {hempstead2004tinybench, title = {TinyBench: The case for a standardized benchmark suite for TinyOS based wireless sensor network devices}, booktitle = {Local Computer Networks, 2004. 29th Annual IEEE International Conference on}, year = {2004}, pages = {585{\textendash}586}, publisher = {IEEE}, organization = {IEEE}, address = {Tampa, FL, USA}, abstract = {The growing wireless sensor network research community lacks a standard method for evaluating hardware platforms. Traditional benchmark suites do not sufficiently address the needs of sensor network designers. This work provides motivation for a benchmark suite and details an approach for benchmarking TinyOS compatible hardware. To aid the development of future hardware architectures, we propose the creation of a standard single node benchmark suite, based on both real applications and "stressmarks." We present sample benchmark results and call for further work in this area.}, url = {https://doi.org/10.1109/LCN.2004.129}, author = {Mark Hempstead and Matt Welsh and David Brooks} } @conference {chin2004evaluating, title = {Evaluating techniques for exploiting instruction slack}, booktitle = {Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on}, year = {2004}, pages = {375{\textendash}378}, publisher = {IEEE}, organization = {IEEE}, address = {San Jose, CA, USA}, abstract = {In many workloads, 25\% to 50\% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efficient, longer latency pipelines or provide dynamically scaled pipelines using multiple clock domains. Issuing instructions with slack to slower pipelines can result in substantial power savings, with minimal performance loss. Considering both dynamic and static power dissipation, we found that by using longer latency pipelines the power of functional unit pipelines decreases by 20\% to 55\% with a performance impact of 0\% to 3\% for SPEC2000 and MediaBench workloads. Dynamic scaling reduces the performance loss in intense multimedia workloads by up to 2\%, but achieves lower power savings.}, url = {10.1109/ICCD.2004.1347949}, author = {Yau Chin and John Sheu and David Brooks} } @conference {li2004understanding, title = {Understanding the energy efficiency of simultaneous multithreading}, booktitle = {Proceedings of the 2004 international symposium on Low power electronics and design}, year = {2004}, pages = {44{\textendash}49}, publisher = {ACM}, organization = {ACM}, address = {Newport Beach, CA, USA}, abstract = {Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of critical importance, and we present modeling extensions to an architectural simulator to allow us to study the power-performance efficiency of SMT. After a thorough design space exploration we find that SMT can provide a performance speedup of nearly 20\% for a wide range of applications with a power overhead of roughly 24\%. Thus, SMT can provide a substantial benefit for energy-efficiency metrics such as ED/sup 2/. We also explore the underlying reasons for the power uplift, analyze the impact of leakage-sensitive process technologies, and discuss our model validation strategy.}, url = {https://doi.org/10.1109/LPE.2004.240758}, author = {Yingmin Li and David Brooks and Zhigang Hu and Kevin Skadron and Pradip Bose} } @conference {hazelwood2004eliminating, title = {Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization}, booktitle = {Proceedings of the 2004 international symposium on Low power electronics and design}, year = {2004}, pages = {326{\textendash}331}, publisher = {ACM}, organization = {ACM}, abstract = {

Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations that stress the power-delivery network. Recent research has focused on hardware-only mechanisms to detect and eliminate these fluctuations. While the solutions have been effective at avoiding operating-range violations, they have done so at a performance penalty to the executing program.

Compilers are well equipped to rearrange instructions such that current fluctuations are less dramatic, with minimal performance implications. Furthermore, a dynamic optimizer can eliminate the problem at run time, avoiding the difficult task of statically predicting voltage emergencies.

This paper proposes complementing existing hardware solutions with additional run-time software to address problematic code sequences that cause recurring voltage swings. Our proposal extends existing hardware techniques to additionally provide feedback to a dynamic optimizer, which can provide a long-term solution, often without impacting the performance of the executing application.

We found that recurring voltage fluctuations do exist in the SPEC2000 benchmarks, and that given very little information from the hardware, a dynamic optimizer can locate and correct many of the recurring voltage emergencies.

}, url = {https://doi.org/10.1145/1013235.1013315}, author = {Kim Hazelwood and David Brooks} } @article {brooks2004high, title = {High level power modeling and analysis}, journal = {International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design}, year = {2004}, publisher = {Association for Computing Machinery, Inc, One Astor Plaza, 1515 Broadway, New York, NY, 10036-5701, USA,}, url = {https://doi.org/10.1145/3246123}, author = {David Brooks and Joerg Henkel} } @article {zyuban2004integrated, title = {Integrated analysis of power and performance for pipelined microprocessors}, journal = {Computers, IEEE Transactions on}, volume = {53}, year = {2004}, pages = {1004{\textendash}1016}, publisher = {IEEE}, abstract = {Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today{\textquoteright}s cost/performance marketplace, modern CPU designs must effectively balance both performance and power dissipation. The choice of pipeline depth and target clock frequency has a critical impact on both of these metrics. In this paper, we describe an optimization methodology based on both analytical models and detailed simulations for power and performance as a function of pipeline depth. Our results for a set of SPEC2000 applications show that, when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of our energy models. Finally, we discuss the potential risks in design quality for overly aggressive or conservative choices of pipeline depth.}, url = {https://doi.org/10.1109/TC.2004.46}, author = {Victor Zyuban and David Brooks and Viji Srinivasan and Michael Gschwind and Pradip Bose and Philip Strenski and Philip Emma} } @conference {ratnayake2004pipelined, title = {Pipelined parallel architecture for high throughput MAP detectors}, booktitle = {2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512)}, volume = {2}, year = {2004}, pages = {II{\textendash}505}, publisher = {IEEE}, organization = {IEEE}, abstract = {A maximum a posteriori probability (MAP) detector based on a forward only algorithm with high throughput is considered in this paper. MAP gives the optimal performance and, with Turbo decoding, can achieve performance close to the channel capacity limits. Deep pipelined architecture for the forward only method is presented and compared with the other throughput-increasing methods. Simulation results based on the iterative MAP-LDPC (low-density parity check) system are shown. Hardware implementation issues that exploit the regularities of the structure are also discussed.}, url = {http://dx.doi.org/10.1109/ISCAS.2004.1329319}, author = {Ratnayake, Ruwan and Gu-Yeon Wei and Kavcic, Aleksandar} } @conference {hanumolu2004jitter, title = {Jitter in high-speed serial and parallel links}, booktitle = {2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512)}, volume = {4}, year = {2004}, pages = {IV{\textendash}425}, publisher = {IEEE}, organization = {IEEE}, address = {Vancouver, BC, Canada}, abstract = {Jitter degrades the performance of both high-speed serial and parallel I/O links by limiting the maximum achievable data-rates. We present analytical expressions to evaluate the effect of jitter on the performance of high-speed links. These expressions enable simple calculation of worst-case voltage and timing margins in the presence of jitter. This analysis is also extended to equalized links. Finally, we show that the limited bandwidth of the channel can amplify high frequency jitter and present means to counteract jitter amplification.}, url = {https://doi.org/10.1109/ISCAS.2004.1329031}, author = {Hanumolu Kumar and Casper Bryan and Mooney Randy and Gu Wei and Moon Ku} } @conference {bae2004mixed, title = {A mixed PLL/DLL architecture for low jitter clock generation}, booktitle = {2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512)}, volume = {4}, year = {2004}, pages = {IV{\textendash}788}, publisher = {IEEE}, organization = {IEEE}, address = {Vancouver, BC, Canada}, abstract = {This paper presents a mixed PLL/DLL architecture for low-jitter clock generation that merges phase-locked loop (PLL) and delay-locked loop (DLL) characteristics. It relies on an interpolator to configure the loop to operate more like a PLL or more like a DLL depending on the interpolator{\textquoteright}s settings. The ability to vary interpolator settings enables wide range control of the clock generator{\textquoteright}s loop bandwidth. Therefore, the loop bandwidth can readily be adjusted to accommodate different noise conditions. A discrete-time Z-domain analysis is provided to illustrate the noise filtering characteristics of the loop in the presence of various noise sources and highlight the potential advantages of the mixed PLL/DLL architecture. Simulation results verify stable operation of the loop designed for a 0.18 /spl mu/m CMOS process.}, url = {10.1109/ISCAS.2004.1329122}, author = {Bae,Yong Cheol and Gu-Yeon Wei} } @article {brooks2004power, title = {Power-performance simulation: design and validation strategies}, journal = {ACM SIGMETRICS Performance Evaluation Review}, volume = {31}, year = {2004}, pages = {13{\textendash}18}, publisher = {ACM}, abstract = {

Microprocessor research and development increasingly relies on detailed simulations to make design choices. As such, the structure, speed, and accuracy of microarchitectural simulators is of critical importance to the field. This paper describes our experiences in building two simulators, using related but distinct approaches.One of the most important attributes of a simulator is its ability to accurately convey design trends as different aspects of the microarchitecture are varied. In this work, we break down accuracy---a broad term--- into two sub-types: relative and absolute accuracy. We then discuss typical abstraction errors in power-performance simulators and show when they do (or do not) affect the design rule choices a user of those simulator might make. By performing this validation study using the Wattch and Power Timer simulators, the work addresses validation issues both broadly and in the specific case of a fairly widely-used simulator.

}, url = {https://doi.org/10.1145/1054907.1054911}, author = {David Brooks and Pradip Bose and Margaret Martonosi} } @conference {fulford2004portable, title = {A portable, low-power, wireless two-lead EKG system}, booktitle = {The 26th Annual International Conference of the IEEE Engineering in Medicine and Biology Society}, volume = {1}, year = {2004}, pages = {2141{\textendash}2144}, publisher = {IEEE}, organization = {IEEE}, abstract = {

Sensor devices ("motes") which integrate an embedded microprocessor, low-power radio and a limited amount of storage have the potential to significantly enhance the provision of emergency medical care. Wearable vital sign sensors can wirelessly monitor patient condition, alerting healthcare providers to changes in status while simultaneously delivering data to a backend archival system for longer-term storage. As part of the CodeBlue initiative at Harvard University, we previously developed a mote-based pulse oximetry module which gathers data from a noninvasive finger sensor and transmits it wirelessly to a base station. To expand the capabilities of the mote for healthcare applications we now introduce EKG on Mica2, the first custom-designed electrocardiograph sensor board to interface with this platform. We additionally present VitalEKG, a collection of software components which allow the capture and wireless transmission of heart activity traces. We present preliminary test results which validate our approach and suggest the feasibility of future enhancements.

}, url = {https://doi.org/10.1109/iembs.2004.1403627}, author = {Fulford RF and Gu Wei and Matt Welsh} } @article {li2004evaluating, title = {Evaluating the thermal efficiency of SMT and CMP architectures}, journal = {IBM TJ Watson Conference on Interaction between Architecture, Circuits, and Compilers}, year = {2004}, abstract = {Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their thermal properties are still poorly understood. This paper uses Turandot, PowerTimer, and HotSpot to evaluate the thermal eff iciency for a Power4/Power5-like core. Our results show that although SMT and CMP exhibit similar peak operating temperatures, the mechanism by which they heat up are quite different. More specifically, SMT heating is primarily caused by localized heating in certain key structures such as the register file, due to increased utilization. On the other hand, CMP heating is mainly caused by the global impact of increased energy output, due to the extra energy of an added core. Because of this difference in heat up machanism, we found that the best thermal management technique is also different for SMT and CMP. Finally, we show that CMP and SMT will scale differently as the contribution of leakage power grows, with CMP suffering from higher leakage due to the second core{\textquoteright}s higher temperature and the exponential temperature-dependence of subthreshold leakage.}, author = {Yingmin Li and K Skadron and Z Hu and David Brooks} } @booklet {brooks2004integrated, title = {Integrated Architectural Level Power-Performance Modeling Toolkit}, year = {2004}, publisher = {DTIC Document}, abstract = {We are currently developing a robust, integrated infrastructure for studying power-performance issues across a range of systems. \ By leveraging a common ISA and shared simulation infrastructure, we will be able to perform apples-to-apples comparisons between processors intended for specific design spaces. \ For example, recently there has been significant attention brought to the idea of reusing microprocessor cores in multiple design spaces. \ In particular, there has been much interest in exploring the possibility of using multiple low-power, embedded processors in blade systems or SMP-on-a-chip designs for server workloads. \ There has also been interest in taking server-class microprocessors and bringing them into use in lower-end systems. \ For example, the processor core of the original POWER4 microprocessor has recently been introduced as the PowerPC970 -- a 64-bit microprocessor for use in blade servers and desktop (and potentially laptop) systems. We utilize the MET/Turandot toolkit originally developed at IBM TJ Watson Research Center as the underlying PowerPC microarchitecture performance simulator [3]. \ Turandot is flexible enough to model a broad range of microarchitectures and has undergone extensive validation [3]. \ In addition, \ Turandot has been augmented with power models to explore power-performance tradeoffs in an internal IBM tool called PowerTimer [4]. Turandot is freely available to the research community through licensing arrangements with IBM, and we are currently working with IBM to develop an external, public release of PowerTimer.\ }, author = {David Brooks} } @conference {wei2003500mhz, title = {A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS}, booktitle = {2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.}, year = {2003}, pages = {464{\textendash}465}, publisher = {IEEE}, organization = {IEEE}, abstract = {Low-jitter clock generation is a critical component for enabling robust high-speed operation of 5Gb/s backplane transceivers. The implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying delay-locked loop (MDLL) is described. The choice depends on the noise characteristics of the input clock source. This MP/DLL design is implemented in a 0.25/spl mu/m CMOS process and operates with a 2.5V supply.}, url = {https://doi.org/10.1109/ISSCC.2003.1234388}, author = {Gu Wei and Stonick T and Weinlader Dan and Sonntag Jeff and Searles Shawn} } @article {brooks2003new, title = {New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors}, journal = {IBM Journal of Research and Development}, volume = {47}, year = {2003}, pages = {653{\textendash}670}, publisher = {IBM}, abstract = {The PowerTimer toolset has been developed for use in early-stage, microarchitecture-level power-performance analysis of microprocessors. The key component of the toolset is a parameterized set of energy functions that can be used in conjunction with any given cycle-accurate microarchitectural simulator. The energy functions model the power consumption of primitive and hierarchically composed building blocks which are used in microarchitecture-level performance models. Examples of structures modeled are pipeline stage latches, queues, buffers and component read/write multiplexers, local clock buffers, register files, and cache array macros. The energy functions can be derived using purely analytical equations that are driven by organizational, circuit, and technology parameters or behavioral equations that are derived from empirical, circuit-level simulation experiments. After describing the modeling methodology, we present analysis results in the context of a current-generation superscalar processor simulator to illustrate the use and effectiveness of such early-stage models. In addition to average power and performance tradeoff analysis, PowerTimer is useful in assessing the typical and worst-case power (or current) swings that occur between successive cycle windows in a given workload execution. Such a characterization of workloads at the early stage of microarchitecture definition helps pinpoint potential inductive noise problems on the voltage rail that can be addressed by designing an appropriate package or by suitably tuning the dynamic power management controls within the processor.}, url = {https://doi.org/10.1147/rd.475.0653}, author = {David Brooks and Pradip Bose and Vijayalakshmi Srinivasan and Michael Gschwind and Philip Emma and Michael Rosenfield} } @article {stonick2003adaptive, title = {An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS}, journal = {IEEE Journal of Solid-State Circuits}, volume = {38}, year = {2003}, pages = {436{\textendash}443}, publisher = {IEEE}, abstract = {This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm/sup 2/ device is implemented in a 0.25 /spl mu/m CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.}, url = {https://doi.org/10.1109/CICC.2002.1012844}, author = {Stonick T and Gu Wei and Sonntag L and Weinlader K} } @article {bose2003early, title = {Early-stage definition of LPX: A low power issue-execute processor}, journal = {Power-Aware Computer Systems}, year = {2003}, pages = {89{\textendash}92}, publisher = {Springer}, abstract = {

We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a vector (SIMD) multimedia extension. The objective of this project is to validate some key new ideas in power-aware microarchitecture techniques, supported by recent advances in circuit design and clocking.

}, url = {https://link.springer.com/chapter/10.1007/3-540-36612-1_1}, author = {P Bose and David Brooks and A Buyuktosunoglu and Cook, P. and K Das and P Emma and M Gschwind and H Jacobson and T Karkhanis and P Kudva} } @conference {joseph2003control, title = {Control techniques to eliminate voltage emergencies in high performance processors}, booktitle = {High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on}, year = {2003}, pages = {79{\textendash}90}, publisher = {IEEE}, organization = {IEEE}, address = {Anaheim, CA, USA}, abstract = {Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effective at reducing average power, many of these techniques have the undesired side-effect of increasing both the variability of power dissipation and the variability of current drawn by the processor This increase in current variability, often referred to as the dI/dt problem, can cause supply voltage fluctuations. Such voltage fluctuations lead to unreliable circuits if not addressed, and increasingly expensive chip packaging techniques are needed to mitigate them. This paper proposes and evaluates a methodology for augmenting packaging techniques for dI/dt with microarchitectural control mechanisms. We discuss the resonant frequencies most relevant to current microprocessor packages, produce and evaluate a "dI/dt stressmark" that exercises the system at its resonant frequency, and characterize the behavior of more mainstream applications. Based on these results plus evaluations of the impact of controller error and delay, our microarchitectural control proposals offer bounds on supply voltage fluctuations, with nearly negligible impact on performance and energy. With the ITRS roadmap predicting aggressive drops in supply voltage and power supply impedances in coming chip generations, novel voltage control techniques will be required to stay on track. Our microarchitectural dI/dt controllers represent a step in this direction.}, url = {https://doi.org/10.1109/HPCA.2003.1183526}, author = {Russ Joseph and David Brooks and Margaret Martonosi} } @article {hanumolu2003analysis, title = {Analysis of PLL clock jitter in high-speed serial links}, journal = {IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing}, volume = {50}, year = {2003}, pages = {879{\textendash}886}, publisher = {IEEE}, author = {Hanumolu Kumar and Casper, Bryan and Mooney Randy and Gu Wei and Moon Ku} } @article {kim2003design, title = {Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach}, journal = {IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing}, volume = {50}, year = {2003}, pages = {860{\textendash}869}, publisher = {IEEE}, author = {Kim, Jaeha and Horowitz, A and Gu Wei} } @conference {srinivasan2002optimizing, title = {Optimizing pipelines for power and performance}, booktitle = {Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on}, year = {2002}, pages = {333{\textendash}344}, publisher = {IEEE}, organization = {IEEE}, abstract = {During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical power-performance model to derive optimal pipeline depth for a superscalar processor. The results are validated and further refined using detailed simulation based analysis. As part of the power-modeling methodology, we have developed equations that model the variation of energy as a function of pipeline depth. Our results using a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models.}, url = {https://doi.org/10.1109/MICRO.2002.1176261}, author = {Viji Srinivasan and David Brooks and Michael Gschwind and Pradip Bose and Victor Zyuban and Philip Strenski and Philip Emma} } @article {martonosi2002architecture, title = {Architecture-level power modeling with Wattch}, journal = {Computer}, volume = {35}, year = {2002}, pages = {64{\textendash}64}, publisher = {IEEE Computer}, author = {M Martonosi and David Brooks and V Tiwari} } @conference {buyuktosunoglu2002power, title = {Power-efficient issue queue design}, booktitle = {Power aware computing}, year = {2002}, pages = {35{\textendash}58}, publisher = {Kluwer Academic Publishers}, organization = {Kluwer Academic Publishers}, abstract = {

Increasing levels of power dissipation threaten to limit the performance gains of future high-end, out-of-order issue microprocessors. Therefore, it is imperative that designers devise techniques that significantly reduce the power dissipation of the key hardware structures on the chip without unduly compromising performance. Such a key structure in out-of-order designs is the issue queue. Although crucial in achieving high performance, the issue queues are often a major contributor to the overall power consumption of the chip, potentially affecting both thermal issues related to hot spots and energy issues related to battery life. In this chapter, we present two techniques that significantly reduce issue queue power while maintaining high performance operation. First, we evaluate the power savings achieved by implementing a CAM/RAM structure for the issue queue as an alternative to the more power-hungry latch-based issue queue used in many designs. We then present the microarchitecture and circuit design of an adaptive issue queue that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. We compare two different dynamic adaptation algorithms that use issue queue utilization and parallelism metrics in order to size the issue queue on-the-fly during execution. Together, these two techniques provide over a 70\% average reduction in issue queue power dissipation for a collection of the SPEC CPU2000 integer benchmarks, with only a 3\% overall performance degradation.

}, url = {https://doi.org/10.1007/978-1-4757-6217-4_3}, author = {Alper Buyuktosunoglu and David Albonesi and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook} } @inbook {wei2002energy, title = {Energy-efficient design of high-speed links}, booktitle = {Power Aware Design Methodologies}, volume = {8}, year = {2002}, pages = {201{\textendash}239}, publisher = {Springer, Boston, MA}, organization = {Springer, Boston, MA}, abstract = {

Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and describes some of the power vs. performance trade-offs associated with various design choices. The chapter then investigates various techniques that a designer may employ to reduce power consumption. Three examples of link designs and link building blocks found in the literature present energy-efficient implementations of these techniques.

}, url = {https://doi.org/10.1007/0-306-48139-1_8}, author = {Gu Wei and Horowitz Mark and Kim, Jaeka} } @report {bosepower, title = {Power-Performance and Power Swing Characterization in Adaptive Microarchitectures}, year = {2002}, institution = {IBM Research}, abstract = {In this paper, we present an analysis of some of the fundamental power-performance tradeoffs in processors that employ adaptive techniques to vary sizes, bandwidths, clock-gating modes and clock frequencies. Initial expectations are set using simple analytical reasoning models. Later, simulation-based data is presented in the context of a simple, low-power super scalar processor prototype (called LPX) that is currently under development as a test vehicle. There are three fundamental issues that we attempt to address in this paper: (a) Does dynamic adaptation - in clocking or microarchitectural resources - help extend the power-performance efficiency range of wider-issue superscalars ? (b) What factors of power and power-density reductions are within practical reach in future adaptive processors ? (c) Does the presence of dynamic adaptation modes cause unacceptably large, worst-case power (or current) swings in affected sub-units ?}, url = {https://dominoweb.draco.res.ibm.com/5762e1ce48772a0285256b800057b82d.html}, author = {Pradip Bose and David Brooks and Viji Srinivasan and Philip Emma} } @article {brooks2001power, title = {Power-performance modeling and tradeoff analysis for a high end microprocessor}, journal = {Power-Aware Computer Systems}, year = {2001}, pages = {126{\textendash}136}, publisher = {Springer}, abstract = {We describe a new power-performance modeling toolkit, developed to aid in the evaluation and definition of future power-efficient, PowerPC TM processors. The base performance models in use in this project are: (a) a fast but cycle-accurate, parameterized research simulator and (b) a slower, pre-RTL reference model that models a specific high-end machine in full, latchaccurate detail. Energy characterizations are derived from real, circuit-level power simulation data. These are then combined to form higher-level energy models that are driven by microarchitecture-level parameters of interest. The overall methodology allows us to conduct power-performance tradeoff studies in defining the follow-on design points within a given product family. We present a few experimental results to illustrate the kinds of tradeoffs one can study using this tool.}, url = {http://dx.doi.org/10.1007/3-540-44572-2_10}, author = {David Brooks and Margaret Martonosi and John Wellman and Pradip Bose} } @mastersthesis {brooks2001design, title = {Design and modeling of power-efficient computer architectures}, year = {2001}, school = {Princeton University}, abstract = {

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and compiler writers, in addition to circuit designers. Most traditional power analysis tools achieve high accuracy by calculating power estimates for designs only after the circuit design, layout, and floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.

This thesis presents a methodology for estimating power dissipation at a much earlier stage in the design cycle and at a much higher level. Watch and PowerTimer are two working examples of the use of this methodology. Both tools provide a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. These tools are 1000X or more faster than existing layout-level power tools, and yet maintain accuracy within 10\% of their estimates as verified using industry tools on leading-edge designs. These tools can allow architects to explore and cull the design space early on and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

This thesis also considers several applications of architectural-level power modeling to propose specific architectural-level power and temperature saving optimizations{\textemdash}value-based clock gating and dynamic thermal management. Value-based clock gating is a technique which exploits the dynamic bitwidth requirements of typical applications to save power within arithmetic units and the memory hierarchy. We have demonstrated that this technique can save roughly 50\% of the power in the integer execution units. With dynamic thermal management, temperature sensors and throttling techniques are combined to adaptively slow down the CPU for extended periods of particularly high-power code sequences. This allows the CPU package and power delivery system to be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

The techniques presented in this thesis represent some of the first work in the area of high-performance, low-power processor design at the architectural level. We hope that this work, and the other research in the area of low-power architectural modeling and design, will help future generations of processor architectures to meet the many new challenges in this area.

}, url = {https://www.proquest.com/docview/251124879?pq-origsite=gscholar\&fromopenview=true}, author = {David Brooks and Margaret, Martonosi (advisor)} } @mastersthesis {wei2001energy, title = {Energy-efficient I/O interface design with adaptive power-supply regulation}, year = {2001}, school = {Stanford University}, type = {phd}, abstract = {This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-/spl mu/m CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2 V.}, url = {https://doi.org/10.1109/4.881205}, author = {Gu Wei} } @article {joseph2001live, title = {Live, runtime power measurements as a foundation for evaluating power/performance tradeoffs}, journal = {Workshop on Complexity Effectice Design WCED, held in conjunction with ISCA}, volume = {28}, year = {2001}, publisher = {Citeseer}, abstract = {Of the many ways one could gauge the complexity-effectiveness of a design or design element, one candidate approach is to consider a design{\textquoteright}s power/performance tradeoffs. This paper describes our early-stage results in a broad effort to evaluate the power-performance tradeoffs of a range of benchmarks and microarchitectures. In particular, this paper presents power data collected on-the-fly on real x86 machines as they execute carefully-constructed microbenchmarks. The microbenchmarks exercise aspects of the system such as data cache and branch predictor. They are parametrically-variable to consider how load dependence, cache miss rate, branch mispredict rate, and branch distance all impact the power and performance of a CPU. For example, from these experiments, we learn that CPU performance increases essentially monotonically with cache hit rate, while CPU power encounters a maximum at roughly 80-90\% cache hit rates. Likewise, we show results demonstrating that performance-neutral issues such as bit populations in the data cache values can display interesting power trends. While the experimental results are preliminary, we feel that the techniques described in this paper will o er a useful foundation for a broad range of power/performance tradeoffs.}, author = {Russ Joseph and David Brooks and Margaret Martonosi} } @article {buyuktosunoglu2001adaptive, title = {An adaptive issue queue for reduced power at high performance}, journal = {Power-Aware Computer Systems}, year = {2001}, pages = {25{\textendash}39}, publisher = {Springer}, abstract = {

Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70\% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56\% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).

}, url = {https://doi.org/10.1007/3-540-44572-2_3}, author = {Alper Buyuktosunoglu and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook and David Albonesi} } @conference {buyuktosunoglu2001circuit, title = {A circuit level implementation of an adaptive issue queue for power-aware microprocessors}, booktitle = {Proceedings of the 11th Great Lakes symposium on VLSI}, year = {2001}, pages = {73{\textendash}78}, publisher = {ACM}, organization = {ACM}, abstract = {Increasing power dissipation has become a major constraint for future per~brmartce gains in the design of microproces- sors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmis- sion gate insertion to provide dynamic low-cost configura- bility of size and speed. A novel circuit structure dynami- cally gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70\% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost neg- ligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56\% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size f{\textyen}om 32 entries (largest possible) to 8 entries (smallest possible in our design).\ }, url = {https://doi.org/10.1145/368122.368807}, author = {Alper Buyuktosunoglu and David Albonesi and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook} } @conference {brooks2001dynamic, title = {Dynamic thermal management for high-performance microprocessors}, booktitle = {High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on}, year = {2001}, pages = {171{\textendash}182}, publisher = {IEEE}, organization = {IEEE}, abstract = {

With the increasing clock rate and transistor count of today{\textquoteright}s microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip{\textquoteright}s rated maximum power dissipation. However system designers still must design thermal heat sinks to withstand the worse-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specifically we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and software implementations. With approximate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

}, url = {https://doi.org/10.1109/HPCA.2001.903261}, author = {David Brooks and Margaret Martonosi} } @article {bose2001modeling, title = {Modeling and Analyzing CPU Power and Performance: Metrics, Methods, and Abstractions}, journal = {Tutorial, ACM SIGMETRICS}, year = {2001}, author = {Pradip Bose and Margaret Martonosi and David Brooks} } @conference {sidiropoulos2000adaptive, title = {Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers}, booktitle = {2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No. 00CH37103)}, year = {2000}, pages = {124{\textendash}127}, publisher = {IEEE}, organization = {IEEE}, author = {Sidiropoulos Stefanos and Liu Dean and Kim Jaeha and Gu Wei and Horowitz Mark} } @conference {brooks2000adaptive, title = {Adaptive thermal management for high-performance microprocessors}, booktitle = {In Workshop on Complexity Effective Design}, year = {2000}, publisher = {Citeseer}, organization = {Citeseer}, author = {David Brooks and Margaret Martonosi} } @article {brooks2000power, title = {Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors}, journal = {Micro, IEEE}, volume = {20}, year = {2000}, pages = {26{\textendash}44}, publisher = {IEEE}, author = {David Brooks and Pradip Bose and Stanley Schuster and Hans Jacobson and Prabhaka Kudva and Alper Buyuktosunoglu and J Wellman and Victor Zyuban and Manish Gupta and Peter Cook} } @article {brooks2000value, title = {Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance}, journal = {ACM Transactions on Computer Systems (TOCS)}, volume = {18}, year = {2000}, pages = {89{\textendash}126}, publisher = {ACM}, author = {David Brooks and Margaret Martonosi} } @article {wei2000variable, title = {A variable-frequency parallel I/O interface with adaptive power-supply regulation}, journal = {IEEE Journal of Solid-State Circuits}, volume = {35}, year = {2000}, pages = {1600{\textendash}1610}, publisher = {IEEE}, author = {Gu Wei and Kim, Jaeha and Liu, Dean and Sidiropoulos, Stefanos and Horowitz, Mark A} } @article {martonosi2000wattch, title = {Wattch: A framework for architectural-level power analysis and optimizations}, journal = {isca}, year = {2000}, pages = {83}, publisher = {ACM Press}, author = {Margaret Martonosi and Vivek Tiwari and David Brooks} } @article {wei1999fully, title = {A fully digital, energy-efficient, adaptive power-supply regulator}, journal = {IEEE Journal of solid-state Circuits}, volume = {34}, year = {1999}, pages = {520{\textendash}528}, publisher = {IEEE}, abstract = {

A voltage scaling technique for energy-efficient operation requires an adaptive power-supply regulator to significantly reduce dynamic power consumption in synchronous digital circuits. A digitally controlled power converter that dynamically tracks circuit performance with a ring oscillator and regulates the supply voltage to the minimum required to operate at a desired frequency is presented. This paper investigates the issues involved in designing a fully digital power converter and describes a design fabricated in a MOSIS 0.8-/spl mu/m process. A variable-frequency digital controller design takes advantage of the power savings available through adaptive supply-voltage scaling and demonstrates converter efficiency greater than 90\% over a dynamic range of regulated voltage levels.

}, url = {https://doi.org/10.1109/4.753685}, author = {Gu Wei and Horowitz Mark} } @conference {brooks1999dynamically, title = {Dynamically exploiting narrow width operands to improve processor power and performance}, booktitle = {High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On}, year = {1999}, pages = {13{\textendash}22}, publisher = {IEEE}, organization = {IEEE}, address = {Orlando, FL, USA}, abstract = {

In general-purpose microprocessors, recent trends have pushed towards 64 bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer problems, however, rarely need the full 64 bit dynamic range these CPUs provide. In fact, another recent instruction set trend has been increased support for sub-word operations (that is, manipulating data in quantities less than the full word size). In particular, most major processor families have introduced "multimedia" instruction set extensions that operate in parallel on several sub-word quantities in the same ALU. This paper notes that across the SPECint95 benchmarks, over half of the integer operation executions require 16 bits or less. With this as motivation, our work proposes hardware mechanisms that dynamically recognize and capitalize on these "narrow-bitwidth" instances. Both optimizations require little additional hardware, and neither requires compiler support. The first, power-oriented, optimization reduces processor power consumption by using aggressive clock gating to turn off portions of integer arithmetic units that will be unnecessary for narrow bitwidth operations. This optimization results in an over 50\% reduction in the integer unit{\textquoteright}s power consumption for the SPECint95 and MediaBench benchmark suites. The second optimization improves performance by merging together narrow integer operations and allowing them to share a single functional unit. Conceptually akin to a dynamic form of MMX, this optimization offers speedups of 4.3\%-6.2\% for SPECint95 and 8.0\%-10.4\% for MediaBench.

}, url = {https://doi.org/10.1109/HPCA.1999.744314}, author = {David Brooks and Margaret Martonosi} } @inbook {brooks1999implementing, title = {Implementing application-specific cache-coherence protocols in configurable hardware}, booktitle = {Network-Based Parallel Computing. Communication, Architecture, and Applications}, year = {1999}, pages = {181{\textendash}195}, publisher = {Springer}, organization = {Springer}, abstract = {

Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best performance, not all parallel machines provide it. Instead, software layers using Shared Virtual Memory (SVM) can be built to enforce coherence at a higher level. In prior work, researchers have studied application-specific cache coherence protocols implemented either in SVM systems or as handlers run by programmable protocol processors. Since the protocols are specialized to the needs of a single application, they can be particularly helpful in reducing the long latencies and processing overhead that sometimes degrade performance in SVM systems. This paper studies implementing application-specific protocols in hardware, but not via an instruction-based protocol processor as is typical. Instead, we consider configurable implementations based on Field-Programmable Gate Arrays (FPGAs). This approach can be faster than software-based techniques and less expensive than some hardware-based techniques. We study one application, appbt, in detail, including a VHDL-level design of the configurable protocol design. We sketch out approaches for other applications as well. Implementing protocol operations in configurable hardware improves communication performance by roughly 11X for a 32-node system. While overall speedups are a more modest 12\% our method is promising because of its flexibility and because it offers a new way of harnessing configurable hardware at the network interface, where it already exists or could be easily added to current systems.

}, url = {https://doi.org/10.1007/10704826_13}, author = {David Brooks and Margaret Martonosi} } @article {leung1998power, title = {Power-Aware Architecture Studies: Omgoing Work at Princeton}, journal = {Power-Driven Microarchitecture Workshop}, year = {1998}, abstract = {Power dissipation limits have emerged as a major constraint in the design of microprocessors. At the low end of the performance spectrum, namely in the world of handheld and portable devices or systems, power has always dominated over performance (execution time) as the primary design issue. Battery life and system cost constraints drive the design team to consider power over performance in such a scenario. Increasingly, however, power is also a key design issue in the workstation and server markets (see Gowan et al.)1 In this high-end arena the increasing microarchitectural complexities, clock frequencies, and die sizes push the chiplevel{\textemdash}and hence the system-level{\textemdash}power consumption to such levels that traditionally air-cooled multiprocessor server boxes may soon need budgets for liquid-cooling or refrigeration hardware. This need is likely to cause a break point{\textemdash}with a step upward{\textemdash}in the ever-decreasing price-performance ratio curve. As such, a design team that considers power consumption and dissipation limits early in the design cycle and can thereby adopt an inherently lower power microarchitectural line will have a definite edge over competing teams.\ Thus far, most of the work done in the area of high-level power estimation has been focused at the register-transfer-level (RTL) description in the processor design flow. Only recently have we seen a surge of interest in estimating power at the microarchitecture definition stage, and specific work on power-efficient microarchitecture design has been reported.2-8 Here, we describe the approach of using energy-enabled performance simulators in early design. We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics.}, author = {Christina Leung and David Brooks and Margaret Martonosi and Douglas Clark} } @article {harris1997fanout, title = {The fanout-of-4 inverter delay metric}, journal = {Unver{\"o}ffentlichtes Manuskript: http://odin. ac. hmc. edu/harris/research/FO4. pdf}, year = {1997}, abstract = {Digital circuit delays vary with feature size, process corner, operating voltage, and junction temperature. Delays are steadily decreasing with advances in process technology, so comparing results reported in nanoseconds between process generations is difficult. This paper proposes using the delay of a fanout-of-4 inverter (FO4) to normalize process and operating condition variations and quantifies how well this normalization works. A novel application of this correlation is a power-reduction technique. Power supply and operating frequency can be regulated on the fly to minimize power while a chip is performing non-critical operations while allowing full-speed operation when necessary. Proposed implementations [1,2,3] rely on a good correlation between ring-oscillator frequency and critical path latency. The tracking of chip delays with FO4 delay determines the necessary extra margin for functionality over process and environmental variation.}, author = {Harris, David and Ho, Ron and Gu Wei and Horowitz Mark} } @conference {wei1996low, title = {A low power switching power supply for self-clocked systems}, booktitle = {Proceedings of 1996 International Symposium on Low Power Electronics and Design}, year = {1996}, pages = {313{\textendash}317}, publisher = {IEEE}, organization = {IEEE}, address = {Monterey, CA, USA}, abstract = {This paper presents a digital power supply controller for variable frequency and voltage circuits. By using a ring oscillator as a method of predicting circuit performance, the regulated voltage is set to the minimum required to operate at a reference frequency which maximizes energy efficiency. Our initial test silicon, implemented with a fixed frequency controller is analyzed and reveals that the controller{\textquoteright}s power consumption is a major limitation for such a design. To make the controller power dissipation scale with the CV/sup 2/f power of the load, we introduce a new architecture with variable frequency control, which allows the controller{\textquoteright}s supply and frequency to scale along with the load device.}, url = {https://doi.org/10.1109/LPE.1996.547531}, author = {Gu Wei and Horowitz Mark} }