@conference {buyuktosunoglu2002power,
	title = {Power-efficient issue queue design},
	booktitle = {Power aware computing},
	year = {2002},
	pages = {35{\textendash}58},
	publisher = {Kluwer Academic Publishers},
	organization = {Kluwer Academic Publishers},
	abstract = {<p>
	Increasing levels of power dissipation threaten to limit the performance gains of future high-end, out-of-order issue microprocessors. Therefore, it is imperative that designers devise techniques that significantly reduce the power dissipation of the key hardware structures on the chip without unduly compromising performance. Such a key structure in out-of-order designs is the issue queue. Although crucial in achieving high performance, the issue queues are often a major contributor to the overall power consumption of the chip, potentially affecting both thermal issues related to hot spots and energy issues related to battery life. In this chapter, we present two techniques that significantly reduce issue queue power while maintaining high performance operation. First, we evaluate the power savings achieved by implementing a CAM/RAM structure for the issue queue as an alternative to the more power-hungry latch-based issue queue used in many designs. We then present the microarchitecture and circuit design of an adaptive issue queue that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. We compare two different dynamic adaptation algorithms that use issue queue utilization and parallelism metrics in order to size the issue queue on-the-fly during execution. Together, these two techniques provide over a 70\% average reduction in issue queue power dissipation for a collection of the SPEC CPU2000 integer benchmarks, with only a 3\% overall performance degradation.
</p>
},
	url = {https://doi.org/10.1007/978-1-4757-6217-4_3},
	author = {Alper Buyuktosunoglu and David Albonesi and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook}
}
@article {buyuktosunoglu2001adaptive,
	title = {An adaptive issue queue for reduced power at high performance},
	journal = {Power-Aware Computer Systems},
	year = {2001},
	pages = {25{\textendash}39},
	publisher = {Springer},
	abstract = {<p>
	Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70\% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56\% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).
</p>
},
	url = {https://doi.org/10.1007/3-540-44572-2_3},
	author = {Alper Buyuktosunoglu and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook and David Albonesi}
}
@conference {buyuktosunoglu2001circuit,
	title = {A circuit level implementation of an adaptive issue queue for power-aware microprocessors},
	booktitle = {Proceedings of the 11th Great Lakes symposium on VLSI},
	year = {2001},
	pages = {73{\textendash}78},
	publisher = {ACM},
	organization = {ACM},
	abstract = {Increasing power dissipation has become a major constraint for future per~brmartce gains in the design of microproces- sors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmis- sion gate insertion to provide dynamic low-cost configura- bility of size and speed. A novel circuit structure dynami- cally gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70\% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost neg- ligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56\% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size f{\textyen}om 32 entries (largest possible) to 8 entries (smallest possible in our design).\&nbsp;},
	url = {https://doi.org/10.1145/368122.368807},
	author = {Alper Buyuktosunoglu and David Albonesi and Stanley Schuster and David Brooks and Pradip Bose and Peter Cook}
}
