@conference {bhardwaj2020comprehensive, title = {A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs}, booktitle = {Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design}, year = {2020}, pages = {145{\textendash}150}, abstract = {

Modern systems-on-chip (SoCs) include not only general-purpose CPUs but also specialized hardware accelerators. Typically, there are three coherence model choices to integrate an accelerator with the memory hierarchy:\ no coherence, coherent with the last-level cache (LLC), and\ private cache based full coherence.\ However, there has been very limited research on finding which coherence models are optimal for the accelerators of a complex many-accelerator SoC. This paper focuses on determining a\ cost-aware coherence interface\ for an SoC and its target application: find the best coherence models for the accelerators that optimize their power and performance, considering both workload characteristics and system-level contention. A novel comprehensive methodology is proposed that uses Bayesian optimization to efficiently find the cost-aware coherence interfaces for SoCs that are modeled using the gem5-Aladdin architectural simulator. For a complete analysis, gem5-Aladdin is extended to support LLC coherence in addition to already-supported no coherence and full coherence. For a heterogeneous SoC targeting applications with varying amount of accelerator-level parallelism, the proposed framework rapidly finds cost-aware coherence interfaces that show significant performance and power benefits over the other commonly-used coherence interfaces.

}, url = {https://doi.org/10.1145/3370748.3406564}, author = {Bhardwaj, Kshitij and Havasi, Marton and Yao, Yuan and David Brooks and Jos{\'e} Lobato and Gu Wei} }