@article {ma2019fully,
	title = {Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights},
	journal = {IEEE Electron Device Letters},
	volume = {40},
	year = {2019},
	pages = {1403{\textendash}1406},
	publisher = {IEEE},
	abstract = {We present a fully CMOS-compatible multilevel non-volatile memory technology, without any special process cost. It is especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency. We use hot carrier injection to program the single-transistor cells, and we conduct charge pumping experiments which identify interfacial traps, rather than bulk oxide traps, as the dominant factor in producing stable I-V shifts. We also derive a new physics-based experimentally verified logarithmic model to explain the rate of interfacial trap generation in large I-V shift regimes where the conventional power-law no longer applies. We fabricate two chips, one using TSMC{\textquoteright}s 16 nm FinFET and the other in 28 nm planar, and show the FinFET cells are more favorable for non-volatile memory due to their better channel control. We store multiple levels in each FinFET cell using a {\textquotedblleft}program and check{\textquotedblright} strategy which sets memory cells{\textquoteright} currents with standard deviations less than 2 μA across a shifting range of over 100 μA. We demonstrate 8 level FinFET cells with extrapolated 10-year charge loss within 10\% at 125 {\textdegree}C.},
	url = {https://doi.org/10.1109/LED.2019.2930212},
	author = {Ma, Siming and Marco Donato and Sae Lee and David Brooks and Gu  Wei}
}
