@conference {whatmough201714,
	title = {14.3 A 28nm SoC with a 1.2 GHz 568nJ/prediction sparse deep-neural-network engine with\&gt; 0.1 timing error rate tolerance for IoT applications},
	booktitle = {2017 IEEE International Solid-State Circuits Conference (ISSCC)},
	year = {2017},
	pages = {242{\textendash}243},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper presents a 28nm SoC with a programmable FC-DNN accelerator design that demonstrates: (1) HW support to exploit data sparsity by eliding unnecessary computations (4{\texttimes} energy reduction); (2) improved algorithmic error tolerance using sign-magnitude number format for weights and datapath computation; (3) improved circuit-level timing violation tolerance in datapath logic via timeborrowing; (4) combined circuit and algorithmic resilience with Razor timing violation detection to reduce energy via VDD scaling or increase throughput via FCLK scaling; and (5) high classification accuracy (98.36\% for MNIST test set) while tolerating aggregate timing violation rates \&gt;10-1. The accelerator achieves a minimum energy of 0.36μJ/pred at 667MHz, maximum throughput at 1.2GHz and 0.57μJ/pred, or a 10\%-margined operating point at 1GHz and 0.58μJ/pred.<br>\&nbsp;},
	url = {https://doi.org/10.1109/ISSCC.2017.7870351},
	author = {Whatmough  N and Sae Lee and Hyunkwang Lee and Saketh Rama and David Brooks and Gu  Wei}
}
