@article {chung2013adc,
	title = {ADC-based backplane receiver design-space exploration},
	journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	volume = {22},
	year = {2013},
	pages = {1539{\textendash}1547},
	publisher = {IEEE},
	abstract = {Demand for higher throughput backplane communications, coupled with a desire for design portability and flexibility, has led to high-speed backplane receivers that use front-end analog-to-digital converters (ADCs) and digital equalization. Unfortunately, power and complexity of such receivers can be high and require careful design. This paper presents a parameterized ADC-based backplane receiver model that facilitates design-space exploration to optimize the tradeoffs between power and performance-an accurate behavioral model of front-end ADCs is presented for performance estimation and detailed power models for the digital equalizer (EQ) blocks are developed for power estimation. Model-based simulations suggest that comparator offset correction resolution is the most critical ADC design parameter when an overall receiver performance is concerned. Further receiver design-space exploration reveals that a Pareto optimal frontier exists, which can be used as a guideline to set the initial receiver configurations depending on a given power and performance constraints.},
	url = {https://doi.org/10.1109/TVLSI.2013.2275742},
	author = {Chung, Hayun and Gu  Wei}
}
