@conference {agrawal2011area,
	title = {Area efficient phase calibration of a 1.6 GHz multiphase DLL},
	booktitle = {2011 IEEE Custom Integrated Circuits Conference (CICC)},
	year = {2011},
	pages = {1{\textendash}4},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL). The calibration scheme employs sub-sampling using a frequency-offset clock with respect to the DLL reference clock, to measure phase-offsets. The phase-correction circuit uses one digital-to-analog converter across eight variable-delay buffers to reduce the area consumption by 62\%. The test-chip, designed in a 130 nm CMOS process, demonstrates a 8-phase 1.6 GHz DLL with a worst-case phase error of 450 fs.},
	url = {https://doi.org/10.1109/CICC.2011.6055345},
	author = {Agrawal, Ankur and Hanumolu, Kumar and Gu  Wei}
}
