@conference {ratnayake2007bit,
	title = {A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders},
	booktitle = {IEEE GLOBECOM 2007-IEEE Global Telecommunications Conference},
	year = {2007},
	pages = {265{\textendash}270},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.},
	url = {http://dx.doi.org/10.1109/GLOCOM.2007.57},
	author = {Ratnayake NS and Haratsch F and Gu  Wei}
}
