@conference {tan2006adaptive,
	title = {Adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator for optimal jitter performance},
	booktitle = {IEEE Custom Integrated Circuits Conference 2006},
	year = {2006},
	pages = {749{\textendash}752},
	publisher = {IEEE},
	organization = {IEEE},
	address = {San Jose, CA, USA},
	abstract = {This paper presents an adaptive-bandwidth mixing PLL/DLL (MX-PDLL) based multi-phase clock generator that can operate as a PLL, DLL, or a mixture of the two. Moreover, this clock generator can be used in a proposed dual-loop CDR to minimize output clock jitter under various noise environments. A test-chip prototype of the MX-PDLL and a 360deg phase rotator was fabricated in a 0.18mum CMOS process, operating off of a 1.8V supply. Experimentally measured results verify that while PLL-mode operation offers the ability to better filter quantization noise from the digital CDR control, shifting towards DLL-mode operation offers the ability to reduce jitter as the amount of on-chip noise increases},
	url = {https://doi.org/10.1109/CICC.2006.320967},
	author = {TanYuan and Gu  Wei}
}
