@conference {agrawal20088,
	title = {A 8 x 5 Gb/s source-synchronous receiver with clock generator phase error correction},
	booktitle = {2008 IEEE Custom Integrated Circuits Conference},
	year = {2008},
	pages = {459{\textendash}462},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40\% and improves receiver timing margins.},
	url = {https://doi.org/10.1109/CICC.2008.4672120},
	author = {Agrawal, Ankur and Hanumolu, Pavan Kumar and Gu-Yeon Wei}
}
