@conference {bae2004mixed,
	title = {A mixed PLL/DLL architecture for low jitter clock generation},
	booktitle = {2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512)},
	volume = {4},
	year = {2004},
	pages = {IV{\textendash}788},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Vancouver, BC, Canada},
	abstract = {This paper presents a mixed PLL/DLL architecture for low-jitter clock generation that merges phase-locked loop (PLL) and delay-locked loop (DLL) characteristics. It relies on an interpolator to configure the loop to operate more like a PLL or more like a DLL depending on the interpolator{\textquoteright}s settings. The ability to vary interpolator settings enables wide range control of the clock generator{\textquoteright}s loop bandwidth. Therefore, the loop bandwidth can readily be adjusted to accommodate different noise conditions. A discrete-time Z-domain analysis is provided to illustrate the noise filtering characteristics of the loop in the presence of various noise sources and highlight the potential advantages of the mixed PLL/DLL architecture. Simulation results verify stable operation of the loop designed for a 0.18 /spl mu/m CMOS process.},
	url = {10.1109/ISCAS.2004.1329122},
	author = {Bae,Yong Cheol and Gu-Yeon Wei}
}
