@conference {tan2006phase,
	title = {Phase mismatch detection and compensation for PLL/DLL based multi-phase clock generator},
	booktitle = {IEEE Custom Integrated Circuits Conference 2006},
	year = {2006},
	pages = {417{\textendash}420},
	publisher = {IEEE},
	organization = {IEEE},
	address = {San Jose, CA, USA},
	abstract = {Device mismatch and systematic imbalances in the physical design can cause static phase mismatch in a PLL/DLL based multi-phase clock generator and degrade performance. This problem gets worse in deep sub-micron technologies. Interleaved transceiver architectures require precise clocking to maximize data rate and minimize bit errors. In this paper, a static phase mismatch compensation scheme for multiple sampling clocks is proposed and tested in an adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator. The proposed charge pump compensator and power efficient phase-averaging network together reduce the static phase mismatch standard deviation by 37\% when operating in DLL mode. A simple and robust duty-cycle correction circuit exhibits a small residual error of 0.65\% across a wide range (36\% to 49\%) of input clock duty-cycle values},
	url = {https://doi.org/10.1109/CICC.2006.320986},
	author = {TanYuan and Gu  Wei}
}
